SPARTAN-II, busy signal

[Amontec Team, Laurent Gau]

Hi all,

Is that possible to put the busy signal (when the FPGA is configuring)
in a float state.

I coupled an ARM7 and a SPARTAN-II, and busy signal of the FPGA is
directly connected to a data_line of the ARM.
As we are doing FPGA configuration over ethernet, busy line corrupt the
ARM when it try to configure the FPGA.

There are two solutions:
-- change the schemetic
-- to be able to put busy line in a float state as an other IO line when
FPGA is programming :

Are there any option in ISE to do that?

Laurent
www.amontec.com

 

[Marc Baker]

The BUSY signal has no programmable options. It is used during Slave
Parallel configuration mode only. If the CCLK rate is under 50 MHz, it will
stay Low during configuration and can be ignored. See the Spartan-II data
sheet at http://www.xilinx.com/bvdocs/publications/ds001_2.pdf for details.

"Amontec Team, Laurent Gauch" wrote:

Hi all,

Is that possible to put the busy signal (when the FPGA is configuring)
in a float state.

I coupled an ARM7 and a SPARTAN-II, and busy signal of the FPGA is
directly connected to a data_line of the ARM.
As we are doing FPGA configuration over ethernet, busy line corrupt the
ARM when it try to configure the FPGA.

There are two solutions:
-- change the schemetic
-- to be able to put busy line in a float state as an other IO line when
FPGA is programming :

Are there any option in ISE to do that?

Laurent
www.amontec.com

--
Marc Baker
Xilinx Applications
(408) 879-5375