P
Peter Rauschert
Guest
Hi all !
Currently I'm working on a design to be implemented by using a
daughterboard, that is set on top of a TI C671x DSK. On this
daughterboards, one Spartan II FPGA ( XC2S200) with Speedgrade -5 and
package PQFP208 is soldered. This one connects directly to the DSP
expansion ports.
As we would like to have efficient data transmissions between DSP and
FPGA there was the idea to implement a 100MHz SBSRAM tnterface for
transmissions between DSP and Spartan II Block Ram. After some
simulations I guess that the dout timings of the BR are the most
critical part and a propper solution could be just found by manual
floorplanning and using a FPGA with speedgrade -6. Since the board
already is soldered, this might be a little problem :-(
Well, as here are some really experienced guys, I would be happy to
get some suggestions that might help me to get this design working.
Thank you very much !!!!
Currently I'm working on a design to be implemented by using a
daughterboard, that is set on top of a TI C671x DSK. On this
daughterboards, one Spartan II FPGA ( XC2S200) with Speedgrade -5 and
package PQFP208 is soldered. This one connects directly to the DSP
expansion ports.
As we would like to have efficient data transmissions between DSP and
FPGA there was the idea to implement a 100MHz SBSRAM tnterface for
transmissions between DSP and Spartan II Block Ram. After some
simulations I guess that the dout timings of the BR are the most
critical part and a propper solution could be just found by manual
floorplanning and using a FPGA with speedgrade -6. Since the board
already is soldered, this might be a little problem :-(
Well, as here are some really experienced guys, I would be happy to
get some suggestions that might help me to get this design working.
Thank you very much !!!!