O
Oliver Mattos
Guest
Hi,
I have a Spartan 6 project with 7 IP cores wanting VFBC connections to a memory controller. My problem is the MPMC configuration tool won't seem to let me do that because the MPMC can't be configured to have that many VFBC connections.
I'm trying to build a picture-in-picture device for HDMI (6 inputs, 1 output).
Is there a way to "chain" memory controllers to achieve this? Alternatively is there a VFBC bus "splitter/arbitrator" to allow me to connect multiple VFBC IO cores to a single MPMC port? I am reasonably certain memory bandwidth will be OK, providing arbitration/buffering is ok.
(I am a bit new to Xilinx EDA tools, and am probably a bit off topic for this group - please be kind!)
I have a Spartan 6 project with 7 IP cores wanting VFBC connections to a memory controller. My problem is the MPMC configuration tool won't seem to let me do that because the MPMC can't be configured to have that many VFBC connections.
I'm trying to build a picture-in-picture device for HDMI (6 inputs, 1 output).
Is there a way to "chain" memory controllers to achieve this? Alternatively is there a VFBC bus "splitter/arbitrator" to allow me to connect multiple VFBC IO cores to a single MPMC port? I am reasonably certain memory bandwidth will be OK, providing arbitration/buffering is ok.
(I am a bit new to Xilinx EDA tools, and am probably a bit off topic for this group - please be kind!)