G
Gladys
Guest
Hi all, I'm new in DDR2, I've read the MIG document UG388 but I don't
quite understand, I'm wondering if anyones could explain me about the
performance of the MCB's internal write/read FIFO datapath? the DDR2
is 16bits wide, and I need one 64bits write port and one 64bits read
port for my implementation, the data to be stored into DDR2 is 48bits
wide, how to implement this?
quite understand, I'm wondering if anyones could explain me about the
performance of the MCB's internal write/read FIFO datapath? the DDR2
is 16bits wide, and I need one 64bits write port and one 64bits read
port for my implementation, the data to be stored into DDR2 is 48bits
wide, how to implement this?