spartan 3an application

Guest
Hello All,

I have designed a counter system with the SPARTAN 3AN board. There two
modules in the design: the timer and the counter itself. The timer
module gets a 50Khz reference signal (from an external device) and
outputs a 50% time window from that signal. So, basically, it is a
window shaper module. The output of the timer module (50% time
windows) gets feed into the counter module. It uses the 50% reference
signal to control the up or down counter system. The pulses come from
another external device which varies with time (maximum repition rate
50 Mhz, but the actual fluxuation is about 30,20,15 Hz) , so the final
count in the counter module will be either negative or positive.
I think I have constructed the system correctly, using the proper flip-
flops and logic, however, the final count keeps going over the
terminal count value that I have set in the counter module when I do
the implementation with the physical devices. Can someone please
mentor me on this project as I am having a lot of issues ...

`timescale 1ns / 1ps
`timescale 1ns / 1ps
module test(MasterCLK, //input master clk
RESET, //input button
fOUTsave, //output
PULSE, //input
ENDCOUNT, //output
StartDevice, //input button
REFpulse,
PWindow); //input

input MasterCLK;
input StartDevice;
input REFpulse;
input RESET;
input PULSE;
input PWindow;
reg Q;
reg Qreset;
reg Qref;
reg QchipE;
output reg ENDCOUNT;
reg [31:0] OUT;
reg [31:0] OUT1;
output reg [31:0] fOUTsave;
reg PULSE_NEW;
wire PULSE_NEW_out;
reg refPULSEsig;


//reg beginCapturing;
//reg [9:0] timer;

and(PULSE_NEW_out, PWindow, PULSE); //pulse is active when PULSE_NEW
and PERIOD is high

always @ (posedge MasterCLK )
// sync inputs, register outputs
begin

//PULSE_NEW<=PULSE;
// 'chip-enable' is synchronized verison of 'start'-button
QchipE <= StartDevice;
// 'reset' is synchronized version of another button
Qreset <= RESET;
// 'reference'- (direction)-input must also be synchronized
Qref <= PWindow;

refPULSEsig <=REFpulse;

// 'chip-enable' allows/disallows clocking
if(QchipE)
Q <= PULSE;
else
begin
Q <= 0;
//timer <= 0;
end
// 'counter-ready' output is cleared at reset, asserted at
200K counts
if(Qreset)
begin
ENDCOUNT <= 0;
//beginCapturing <= 0;
end
else if(OUT >= 200_000/*_000*/)
ENDCOUNT <= 1;
// accumulated count is registered out after 'ENDCOUNT'
asserts
if(ENDCOUNT)
begin
fOUTsave <= OUT1;
QchipE <= 0; //disable the device, no more pulses into the
system
end
else
fOUTsave <=0;
end
//////////////////////////////////////////////
// counter logic
always @ (posedge Q , posedge Qreset) //pulse
begin
if(Qreset)
begin
OUT <= 0; // zeroed at reset
OUT1 <= 0; //zeroed at reset
end
else
begin
if(Qref & refPULSEsig /*& beginCapturing*/)
begin
OUT1 <= OUT1 + 1'b1; //count UP for REF=1
OUT <= OUT + 1'b1; // count ALL pulses
end
else if (Qref & ~refPULSEsig /*& beginCapturing*/)
begin
OUT1 <= OUT1 - 1'b1; //and DOWN for REF = 0
OUT <= OUT + 1'b1; // count ALL pulses
end
/*else
begin
OUT <= OUT; // hold for other states of inputs
OUT1 <= OUT1; //hold for other states of inputs
end
*/
end
end

endmodule
//////////////////////////////////////////////

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:47:19 01/27/2009
// Design Name:
// Module Name: timer
// Project Name:
// Target Devices:
// Tool versions:
// Description: this module requires a 50Mhz clock signal, located on
the SN3AN board,
// a 50 Khz reference signal, from the Hinds Photoelastic modulator
device, a reset signal
// and outputs a period signal, which is used to control the updown
counter and the Window
// signal, which is used to control the pulse signal
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timer( tMasterCLK, Reference, period, Reset, Window );

input tMasterCLK; //155.52 Mhz system clock
reg RefSync;
input Reference; //50 Khz reference clock
reg RefSyncDelayed;
output reg Window;
output reg period;
input Reset;
reg [31:0] countera;

always @ (posedge tMasterCLK)
begin


if (Reset) begin


// Zap everything on power-up reset
RefSync <= 0;
RefSyncDelayed <= 0;
countera <= 0;
period <= 0;
Window <= 0;

end
else
begin


// Resynchronize Reference, and create a
// delayed version so we can edge-detect it.
RefSync<=Reference;
RefSyncDelayed <= RefSync;


// Manage the counter. Normally it counts
// in the sequence 0,1,....100,101,0,1...
// but as we'll see later this count may be
// aborted by a rising edge on Reference.
//
/*
if (countera == 1999)
countera <= 0;

else */
countera<=countera+1'b1;

// Devices senses which signal to transmit
// depending on the reference signal
// Generate Window and Period outputs as a function
// of counter and the reference singal; but, like the counter,
// they may be reset
// by a rising edge on Reference - see later.
//

if(~RefSyncDelayed | RefSyncDelayed) //low phase
begin
case (countera)
//1: period <= 1;
400: Window <= 1;
1200: Window <= 0; // timeout on Window
//490: period <= 0; // timeout on period
endcase
end
/*else
begin
case (countera)
//1: period <= 1;
400: Window <= 1;
1000: Window <= 0; // timeout on Window
//490: period <= 0;
endcase
end
*/

// When Reference rises, most of this behaviour is
// overridden and the whole thing is reset.
//
if (RefSync & !RefSyncDelayed | !RefSync & RefSyncDelayed) //
rising edge or falling edge
begin
countera <= 0; //reset counter
period <= 0; //reset period flip-flop
Window <= 0;
end

end
end
endmodule

module SystemDPC( CLK, RESET, PMT, END, START_COUNTER, PEM, OUTPUT);

input CLK;
input RESET;
input PMT;
output END;
input START_COUNTER;
input PEM;
output [31:0] OUTPUT;
//output LOCKED;

wire PULSE_WINDOW;
wire PEM_WINDOW;
wire clk_o_buff;
wire clk_2x;
wire clk_2x_buff;
wire pmt_buff;
wire wire_reset;
wire locked;
wire clk0_buff;
wire clk0_buffO;
wire masterCLK;


/*
dcmphoton u0(.CLKIN_IN(CLK),
.RST_IN(wire_reset),
.CLK0_OUT(clk_o_buff),
.CLK2X_OUT(clk_2x_buff),
.LOCKED_OUT(locked));

*/

IBUFG U0_BUFF1(.I(PMT) , .O(pmt_buff));
IBUFG U0_BUFF2(.I(RESET) , .O(wire_reset));

/*assign LOCKED = locked;*/

//and( masterCLK,clk_2x_buff,locked); //when LOCKED is asserted then
give control to the DLL

test counterDPC (.MasterCLK(/*clk_2x_buff*/CLK), //155.52Mhz input
master clk
.RESET(wire_reset), //input button
.fOUTsave(OUTPUT), //output
.PULSE (pmt_buff), //input
.ENDCOUNT (END), //output
.StartDevice (START_COUNTER), //input button
.REFpulse(/*PEM_WINDOW*/PEM), //input pulse window
.PWindow(PULSE_WINDOW)); //input reference window

timer timeDPC (.tMasterCLK(/*clk_o_buff*/CLK), //155.52 Mhz input
master clkdll
.Reference(PEM), //50 Khz input reference
/*.period(PEM_WINDOW), //output new reference signal*/
.Reset(wire_reset), //input resest
.Window(PULSE_WINDOW) ); //output new pulse window

endmodule
 
Hi Uranium,

Your code is really difficult to read with all the varying indentations.
There's also quite a lot of commented code snippets.

The chances, that somebody helps you are probably higher if you send a
cleaned up version of your code once more.

Perhaps you should break down your problem and re-explain it.

So your FPGA is clocked with 50MHz?
One input is a 50kHz signal?
When this signals is one, you count up and if it's 0 you count down.
Is it this?

Let's assume I am right.
Let's assume, the 50kHz signal is not exactly symmetric and would vary
by ONLY ONE clock cycle. (1 is there for 501 cycles and 0 for 499 cycles).

Then you would count up by 501 and count down by 499 per 50KHz period,
(wich results in counting up by 2.

50KHz means, that you have 50,000 of these periods per second. So your
counter will overflow very rapidly.

What I would do is increment the counter and just display the upper digits.

Did you try to simulate the logic?
If yes, you could send the code, that you simuated. It might helpt to
understand the issue.

bye


N

uraniumore238@gmail.com wrote:
Hello All,

I have designed a counter system with the SPARTAN 3AN board. There two
modules in the design: the timer and the counter itself. The timer
module gets a 50Khz reference signal (from an external device) and
outputs a 50% time window from that signal. So, basically, it is a
window shaper module. The output of the timer module (50% time
windows) gets feed into the counter module. It uses the 50% reference
signal to control the up or down counter system. The pulses come from
another external device which varies with time (maximum repition rate
50 Mhz, but the actual fluxuation is about 30,20,15 Hz) , so the final
count in the counter module will be either negative or positive.
I think I have constructed the system correctly, using the proper flip-
flops and logic, however, the final count keeps going over the
terminal count value that I have set in the counter module when I do
the implementation with the physical devices. Can someone please
mentor me on this project as I am having a lot of issues ...

`timescale 1ns / 1ps
`timescale 1ns / 1ps
module test(MasterCLK, //input master clk
RESET, //input button
fOUTsave, //output
PULSE, //input
ENDCOUNT, //output
StartDevice, //input button
REFpulse,
PWindow); //input

input MasterCLK;
input StartDevice;
input REFpulse;
input RESET;
input PULSE;
input PWindow;
reg Q;
reg Qreset;
reg Qref;
reg QchipE;
output reg ENDCOUNT;
reg [31:0] OUT;
reg [31:0] OUT1;
output reg [31:0] fOUTsave;
reg PULSE_NEW;
wire PULSE_NEW_out;
reg refPULSEsig;


//reg beginCapturing;
//reg [9:0] timer;

and(PULSE_NEW_out, PWindow, PULSE); //pulse is active when PULSE_NEW
and PERIOD is high

always @ (posedge MasterCLK )
// sync inputs, register outputs
begin

//PULSE_NEW<=PULSE;
// 'chip-enable' is synchronized verison of 'start'-button
QchipE <= StartDevice;
// 'reset' is synchronized version of another button
Qreset <= RESET;
// 'reference'- (direction)-input must also be synchronized
Qref <= PWindow;

refPULSEsig <=REFpulse;

// 'chip-enable' allows/disallows clocking
if(QchipE)
Q <= PULSE;
else
begin
Q <= 0;
//timer <= 0;
end
// 'counter-ready' output is cleared at reset, asserted at
200K counts
if(Qreset)
begin
ENDCOUNT <= 0;
//beginCapturing <= 0;
end
else if(OUT >= 200_000/*_000*/)
ENDCOUNT <= 1;
// accumulated count is registered out after 'ENDCOUNT'
asserts
if(ENDCOUNT)
begin
fOUTsave <= OUT1;
QchipE <= 0; //disable the device, no more pulses into the
system
end
else
fOUTsave <=0;
end
//////////////////////////////////////////////
// counter logic
always @ (posedge Q , posedge Qreset) //pulse
begin
if(Qreset)
begin
OUT <= 0; // zeroed at reset
OUT1 <= 0; //zeroed at reset
end
else
begin
if(Qref & refPULSEsig /*& beginCapturing*/)
begin
OUT1 <= OUT1 + 1'b1; //count UP for REF=1
OUT <= OUT + 1'b1; // count ALL pulses
end
else if (Qref & ~refPULSEsig /*& beginCapturing*/)
begin
OUT1 <= OUT1 - 1'b1; //and DOWN for REF = 0
OUT <= OUT + 1'b1; // count ALL pulses
end
/*else
begin
OUT <= OUT; // hold for other states of inputs
OUT1 <= OUT1; //hold for other states of inputs
end
*/
end
end

endmodule
//////////////////////////////////////////////

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:47:19 01/27/2009
// Design Name:
// Module Name: timer
// Project Name:
// Target Devices:
// Tool versions:
// Description: this module requires a 50Mhz clock signal, located on
the SN3AN board,
// a 50 Khz reference signal, from the Hinds Photoelastic modulator
device, a reset signal
// and outputs a period signal, which is used to control the updown
counter and the Window
// signal, which is used to control the pulse signal
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timer( tMasterCLK, Reference, period, Reset, Window );

input tMasterCLK; //155.52 Mhz system clock
reg RefSync;
input Reference; //50 Khz reference clock
reg RefSyncDelayed;
output reg Window;
output reg period;
input Reset;
reg [31:0] countera;

always @ (posedge tMasterCLK)
begin


if (Reset) begin


// Zap everything on power-up reset
RefSync <= 0;
RefSyncDelayed <= 0;
countera <= 0;
period <= 0;
Window <= 0;

end
else
begin


// Resynchronize Reference, and create a
// delayed version so we can edge-detect it.
RefSync<=Reference;
RefSyncDelayed <= RefSync;


// Manage the counter. Normally it counts
// in the sequence 0,1,....100,101,0,1...
// but as we'll see later this count may be
// aborted by a rising edge on Reference.
//
/*
if (countera == 1999)
countera <= 0;

else */
countera<=countera+1'b1;

// Devices senses which signal to transmit
// depending on the reference signal
// Generate Window and Period outputs as a function
// of counter and the reference singal; but, like the counter,
// they may be reset
// by a rising edge on Reference - see later.
//

if(~RefSyncDelayed | RefSyncDelayed) //low phase
begin
case (countera)
//1: period <= 1;
400: Window <= 1;
1200: Window <= 0; // timeout on Window
//490: period <= 0; // timeout on period
endcase
end
/*else
begin
case (countera)
//1: period <= 1;
400: Window <= 1;
1000: Window <= 0; // timeout on Window
//490: period <= 0;
endcase
end
*/

// When Reference rises, most of this behaviour is
// overridden and the whole thing is reset.
//
if (RefSync & !RefSyncDelayed | !RefSync & RefSyncDelayed) //
rising edge or falling edge
begin
countera <= 0; //reset counter
period <= 0; //reset period flip-flop
Window <= 0;
end

end
end
endmodule

module SystemDPC( CLK, RESET, PMT, END, START_COUNTER, PEM, OUTPUT);

input CLK;
input RESET;
input PMT;
output END;
input START_COUNTER;
input PEM;
output [31:0] OUTPUT;
//output LOCKED;

wire PULSE_WINDOW;
wire PEM_WINDOW;
wire clk_o_buff;
wire clk_2x;
wire clk_2x_buff;
wire pmt_buff;
wire wire_reset;
wire locked;
wire clk0_buff;
wire clk0_buffO;
wire masterCLK;


/*
dcmphoton u0(.CLKIN_IN(CLK),
.RST_IN(wire_reset),
.CLK0_OUT(clk_o_buff),
.CLK2X_OUT(clk_2x_buff),
.LOCKED_OUT(locked));

*/

IBUFG U0_BUFF1(.I(PMT) , .O(pmt_buff));
IBUFG U0_BUFF2(.I(RESET) , .O(wire_reset));

/*assign LOCKED = locked;*/

//and( masterCLK,clk_2x_buff,locked); //when LOCKED is asserted then
give control to the DLL

test counterDPC (.MasterCLK(/*clk_2x_buff*/CLK), //155.52Mhz input
master clk
.RESET(wire_reset), //input button
.fOUTsave(OUTPUT), //output
.PULSE (pmt_buff), //input
.ENDCOUNT (END), //output
.StartDevice (START_COUNTER), //input button
.REFpulse(/*PEM_WINDOW*/PEM), //input pulse window
.PWindow(PULSE_WINDOW)); //input reference window

timer timeDPC (.tMasterCLK(/*clk_o_buff*/CLK), //155.52 Mhz input
master clkdll
.Reference(PEM), //50 Khz input reference
/*.period(PEM_WINDOW), //output new reference signal*/
.Reset(wire_reset), //input resest
.Window(PULSE_WINDOW) ); //output new pulse window

endmodule
Click to expand...
 
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