Spartan 3 Xilinx IO Standards

[Brad Smallridge]

Can anyone point me to a tutorial or explanation of the IO standards? And
how to set the default? Seems as if the synthesis tool has assigned LVCMOS25
as the default setting although I don't recall setting this standard. As my
IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33?

Additionally in the PACE windows under Design Object List there is a section
with Groups listed. Not sure what this is for, however, I have a group
listed with no ( # 0) items in the group for a symbol I recall that I
deleted from the VHDL code a long time ago. How do I get rid of this old
group?

Thanks,

Brad

 

[Narasimha]

Hi,

Select any pin under "Design Object List - I/O Pin" window in PACE and
then right-click. You'd then get an option to set the I/O standard for
that pin.

You can do the same by selecting multiple signals.

Narasimha.

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10i1rel5f76hm67@corp.supernews.com>...

Can anyone point me to a tutorial or explanation of the IO standards? And
how to set the default? Seems as if the synthesis tool has assigned LVCMOS25
as the default setting although I don't recall setting this standard. As my
IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33?

Additionally in the PACE windows under Design Object List there is a section
with Groups listed. Not sure what this is for, however, I have a group
listed with no ( # 0) items in the group for a symbol I recall that I
deleted from the VHDL code a long time ago. How do I get rid of this old
group?

Thanks,

Brad

 

[Narasimha]

Hi,

Refer to....
http://www1.idt.com/pcms/tempDocs/AN_230.pdf

It gives a fairly good introduction to different I/O standards.

Narasimha.

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10i1rel5f76hm67@corp.supernews.com>...

Can anyone point me to a tutorial or explanation of the IO standards? And
how to set the default? Seems as if the synthesis tool has assigned LVCMOS25
as the default setting although I don't recall setting this standard. As my
IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33?

Additionally in the PACE windows under Design Object List there is a section
with Groups listed. Not sure what this is for, however, I have a group
listed with no ( # 0) items in the group for a symbol I recall that I
deleted from the VHDL code a long time ago. How do I get rid of this old
group?

Thanks,

Brad

 

[Brad Smallridge]

Thanks for the article, Narasimha.

Still need information about (or if possible) to set the default IO
standard, getting rid of an old group, and it just occured to me that I am
assuming that the 33 after LVCMOS refers to the Vcco but I never confirmed
that. Might it be something else like the Voh?

Brad

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:<10i1rel5f76hm67@corp.supernews.com>...
Can anyone point me to a tutorial or explanation of the IO standards?
And
how to set the default? Seems as if the synthesis tool has assigned
LVCMOS25
as the default setting although I don't recall setting this standard.
As my
IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33?

Additionally in the PACE windows under Design Object List there is a
section
with Groups listed. Not sure what this is for, however, I have a group
listed with no ( # 0) items in the group for a symbol I recall that I
deleted from the VHDL code a long time ago. How do I get rid of this
old
group?

Thanks,

Brad

 

[Narasimha]

Brad,

These FPGA vendors never make our life simpler. LVCMOS33 is supposed
to refer to 3.3V LVCMOS I/O Standard. I too am a little confused on
this. Recently, on a Lattice CPLD I was using, the tool selected the
default i/o standard as lvcmos18. I generated the jed file and tested
and everything was running cool. Only later did I realise that i
selected 1.8v io standard on the cpld whereas all the ios on my board
are 3.3v I think the cpld didnt burn because it requires a VCCIO
and that is 3.3V....

I know how to set the default io standard option in Lattice
constraints file. For xilinx.... will let ya know when I know it
myself.

Narasimha.

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10i4ems19um78ed@corp.supernews.com>...

Thanks for the article, Narasimha.

Still need information about (or if possible) to set the default IO
standard, getting rid of an old group, and it just occured to me that I am
assuming that the 33 after LVCMOS refers to the Vcco but I never confirmed
that. Might it be something else like the Voh?

Brad