Spartan 3 pinout typo?

J

Jake Janovetz

Guest
Hi folks-

This isn't a significant note, but it seems there is a slight typo in
the PQ208 package pinout for the Spartan 3. Namely, Bank 1 includes
the following that I believe should be listed as Bank 0:

IO_L32N_0/GCLK7
IO_L32P_0/GCLK6

Although the suffix (_0) indicates they belong in Bank 0, I wanted to
make sure they follow Bank 0 power supplies. Also, the table at the
end of the listing puts two GCLKs in Bank0 and two in Bank1, so that
seems to reinforce the typo.

Correction?

Jake
 
You are correct. The pin name and pin number in the data sheet is correct
as is the PQ208 footprint diagram. As you described, the "_0" suffix
indicates that the pin belongs to I/O bank 0.

The mistake in the data sheet is strictly the bank indication in the pinout
table. This is being corrected as I write and should be posted on
www.xilinx.com by no later than early next week.

Please accept my apologies for any inconvenience this might have caused.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"Jake Janovetz" <jakespambox@yahoo.com> wrote in message
news:d6ad3144.0310082043.43d07d9a@posting.google.com...
Hi folks-

This isn't a significant note, but it seems there is a slight typo in
the PQ208 package pinout for the Spartan 3. Namely, Bank 1 includes
the following that I believe should be listed as Bank 0:

IO_L32N_0/GCLK7
IO_L32P_0/GCLK6

Although the suffix (_0) indicates they belong in Bank 0, I wanted to
make sure they follow Bank 0 power supplies. Also, the table at the
end of the listing puts two GCLKs in Bank0 and two in Bank1, so that
seems to reinforce the typo.

Correction?

Jake
Click to expand...
 
The Spartan-3 pinout tables have now been updated to correct this mistake.
The mistake in the data sheet is strictly the bank indication in the pinout
table. The pin name and pin number in the data sheet is correct as is the
PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available via
either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf

Spartan-3 Complete Data Sheet (All four modules)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

The electronic ASCII-text footprint tables were not affected by this
mistake.
http://direct.xilinx.com/bvdocs/publications/s3_pin.zip

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


"Jake Janovetz" <jakespambox@yahoo.com> wrote in message
news:d6ad3144.0310082043.43d07d9a@posting.google.com...
Hi folks-

This isn't a significant note, but it seems there is a slight typo in
the PQ208 package pinout for the Spartan 3. Namely, Bank 1 includes
the following that I believe should be listed as Bank 0:

IO_L32N_0/GCLK7
IO_L32P_0/GCLK6

Although the suffix (_0) indicates they belong in Bank 0, I wanted to
make sure they follow Bank 0 power supplies. Also, the table at the
end of the listing puts two GCLKs in Bank0 and two in Bank1, so that
seems to reinforce the typo.

Correction?

Jake
Click to expand...
 
"Steven K. Knapp" wrote:
The Spartan-3 pinout tables have now been updated to correct this mistake.
The mistake in the data sheet is strictly the bank indication in the pinout
table. The pin name and pin number in the data sheet is correct as is the
PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available via
either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf

Spartan-3 Complete Data Sheet (All four modules)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

The electronic ASCII-text footprint tables were not affected by this
mistake.
http://direct.xilinx.com/bvdocs/publications/s3_pin.zip
Click to expand...
Steven,

I am looking at partial/modular reconfiguration in Spartan 3 and I
realize that there are some issues with IO that I am not sure how to
resolve. To get an understanding of how to approach the problem I need
to know what IO pads and pins are mapped to what CLB columns. I am
looking at using the XC3S400 in the 456 pin BGA package. Where can I
get info on how the IOs are mapped to the CLB columns?


--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Steven-

Thanks for the quick response. It seems you corrected the other
(similar) bank indication problems. It didn't matter much, but was a
bit confusing at first.

Jake


"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<bmfb4q$g391@cliff.xsj.xilinx.com>...
The Spartan-3 pinout tables have now been updated to correct this mistake.
The mistake in the data sheet is strictly the bank indication in the pinout
table. The pin name and pin number in the data sheet is correct as is the
PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available via
either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf

Spartan-3 Complete Data Sheet (All four modules)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

The electronic ASCII-text footprint tables were not affected by this
mistake.
http://direct.xilinx.com/bvdocs/publications/s3_pin.zip

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


"Jake Janovetz" <jakespambox@yahoo.com> wrote in message
news:d6ad3144.0310082043.43d07d9a@posting.google.com...
Hi folks-

This isn't a significant note, but it seems there is a slight typo in
the PQ208 package pinout for the Spartan 3. Namely, Bank 1 includes
the following that I believe should be listed as Bank 0:

IO_L32N_0/GCLK7
IO_L32P_0/GCLK6

Although the suffix (_0) indicates they belong in Bank 0, I wanted to
make sure they follow Bank 0 power supplies. Also, the table at the
end of the listing puts two GCLKs in Bank0 and two in Bank1, so that
seems to reinforce the typo.

Correction?

Jake
Click to expand...
 
rickman wrote:

"Steven K. Knapp" wrote:

The Spartan-3 pinout tables have now been updated to correct this mistake.
The mistake in the data sheet is strictly the bank indication in the pinout
table. The pin name and pin number in the data sheet is correct as is the
PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available via
either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf

Spartan-3 Complete Data Sheet (All four modules)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

The electronic ASCII-text footprint tables were not affected by this
mistake.
http://direct.xilinx.com/bvdocs/publications/s3_pin.zip

Steven,

I am looking at partial/modular reconfiguration in Spartan 3 and I
realize that there are some issues with IO that I am not sure how to
resolve. To get an understanding of how to approach the problem I need
to know what IO pads and pins are mapped to what CLB columns. I am
looking at using the XC3S400 in the 456 pin BGA package. Where can I
get info on how the IOs are mapped to the CLB columns?
Click to expand...
The relative location of pins to CLBs can be seen graphically in PACE or put into
a text file using "partgen -v xc3s400fg456"

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
--
Marc Baker
Xilinx Applications
(408) 879-5375
 
Marc Baker wrote:
rickman wrote:

"Steven K. Knapp" wrote:

The Spartan-3 pinout tables have now been updated to correct this mistake.
The mistake in the data sheet is strictly the bank indication in the pinout
table. The pin name and pin number in the data sheet is correct as is the
PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available via
either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf

Spartan-3 Complete Data Sheet (All four modules)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

The electronic ASCII-text footprint tables were not affected by this
mistake.
http://direct.xilinx.com/bvdocs/publications/s3_pin.zip

Steven,

I am looking at partial/modular reconfiguration in Spartan 3 and I
realize that there are some issues with IO that I am not sure how to
resolve. To get an understanding of how to approach the problem I need
to know what IO pads and pins are mapped to what CLB columns. I am
looking at using the XC3S400 in the 456 pin BGA package. Where can I
get info on how the IOs are mapped to the CLB columns?

The relative location of pins to CLBs can be seen graphically in PACE or put into
a text file using "partgen -v xc3s400fg456"
Click to expand...
I think you have a leg up on me. I am not familiar with a program
called PACE. I am guessing that is the chip editor? If so, I do not
currently have the full ISE tools and so do not have the chip editor.
How else can I get this file?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Hi Mr. Collins,

I sent the complete file to your personal E-mail address.

If you have the tools, executing "partgen -v xc3s400fg456" generates an
ASCII text file called "3s400fg456.pkg".

A snippet from the file is shown below, just to provide some context on
the fields.

pin PAD2 B4 0 IO_L01N_0/VRP_0 X1Y63 115S
0
pin PAD3 A4 0 IO_L01P_0/VRN_0 X1Y63 115M
0

<type> <pad number> <package pin number> <bank> <pin name>
<closest CLB location> <LVDS pair info> <?>

My apologies, I didn't see your original reply to the last posting on this
thread.

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F96E9F1.AD9558D5@yahoo.com...
Marc Baker wrote:

rickman wrote:

"Steven K. Knapp" wrote:

The Spartan-3 pinout tables have now been updated to correct this
mistake.
The mistake in the data sheet is strictly the bank indication in the
pinout
table. The pin name and pin number in the data sheet is correct as
is the
PQ208 footprint diagram.

The correct information for the PQ208 footprint table is available
via
either of the following two links.

Spartan-3 1.2V FPGA Pinout Descriptions (pinout tables only)
http://direct.xilinx.com/bvdocs/publications/ds099-4.pdf

Spartan-3 Complete Data Sheet (All four modules)
http://direct.xilinx.com/bvdocs/publications/ds099.pdf

The electronic ASCII-text footprint tables were not affected by this
mistake.
http://direct.xilinx.com/bvdocs/publications/s3_pin.zip

Steven,

I am looking at partial/modular reconfiguration in Spartan 3 and I
realize that there are some issues with IO that I am not sure how to
resolve. To get an understanding of how to approach the problem I
need
to know what IO pads and pins are mapped to what CLB columns. I am
looking at using the XC3S400 in the 456 pin BGA package. Where can I
get info on how the IOs are mapped to the CLB columns?

The relative location of pins to CLBs can be seen graphically in PACE or
put into
a text file using "partgen -v xc3s400fg456"

I think you have a leg up on me. I am not familiar with a program
called PACE. I am guessing that is the chip editor? If so, I do not
currently have the full ISE tools and so do not have the chip editor.
How else can I get this file?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
 
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