T
Tobias Kahre
Guest
On a PCI Card I got a XC3SD1800A-4FGG676C.
While trying to establish a differential output pair on Pins K23,K22, i got the following message:
----------------------------------------------------------------------------
ERRORack:1107 - Pack was unable to combine the symbols listed below into a
single DIFFMTB component because the site type selected is not compatible.
The root cause of failure is that the IOSTANDARD=LVDS_33 property is only
supported in the TOP and BOTTOM IO banks.
Further explanation:
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
DIFFMTB was chosen because the IO contains symbols and/or properties
consistent with differential master usage and a IOSTANDARD=LVDS_33 property.
Please double check that the types of logic elements and all of their
relevant properties and configuration options are compatible with the
physical site type of the constraint.
-----------------------------------------------------------------------------
The PCI Board Vendor claims in his manual, that these pins are suited for usage as a diff pair.
The Xilinx Datasheets do not say anything against this, IMHO.
The Xilinx mapping tool seems to have a different opinion
What am I doing wrong? Would a DIFFMLR be more suited for Banks 1 and 3?
Lost Regards
Tobias
p.s:
from UCF File:
--------------
NET "dig_io[30]" IOSTANDARD = LVDS_33;
NET "dig_io[30]" LOC = K23;
NET "dig_io[31]" IOSTANDARD = LVDS_33;
NET "dig_io[31]" LOC = K22;
from top level file:
--------------------
buf_o_pxlclk: obufds port map (i => o_pxl_clk, o=> dig_io(30), ob => dig_io(31) );
While trying to establish a differential output pair on Pins K23,K22, i got the following message:
----------------------------------------------------------------------------
ERRORack:1107 - Pack was unable to combine the symbols listed below into a
single DIFFMTB component because the site type selected is not compatible.
The root cause of failure is that the IOSTANDARD=LVDS_33 property is only
supported in the TOP and BOTTOM IO banks.
Further explanation:
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
DIFFMTB was chosen because the IO contains symbols and/or properties
consistent with differential master usage and a IOSTANDARD=LVDS_33 property.
Please double check that the types of logic elements and all of their
relevant properties and configuration options are compatible with the
physical site type of the constraint.
-----------------------------------------------------------------------------
The PCI Board Vendor claims in his manual, that these pins are suited for usage as a diff pair.
The Xilinx Datasheets do not say anything against this, IMHO.
The Xilinx mapping tool seems to have a different opinion
What am I doing wrong? Would a DIFFMLR be more suited for Banks 1 and 3?
Lost Regards
Tobias
p.s:
from UCF File:
--------------
NET "dig_io[30]" IOSTANDARD = LVDS_33;
NET "dig_io[30]" LOC = K23;
NET "dig_io[31]" IOSTANDARD = LVDS_33;
NET "dig_io[31]" LOC = K22;
from top level file:
--------------------
buf_o_pxlclk: obufds port map (i => o_pxl_clk, o=> dig_io(30), ob => dig_io(31) );