Spartan 3 DiffPairs restricted to Banks 0 and 2?

T

Tobias Kahre

Guest
On a PCI Card I got a XC3SD1800A-4FGG676C.
While trying to establish a differential output pair on Pins K23,K22, i got the following message:

----------------------------------------------------------------------------
ERROR:pack:1107 - Pack was unable to combine the symbols listed below into a
single DIFFMTB component because the site type selected is not compatible.
The root cause of failure is that the IOSTANDARD=LVDS_33 property is only
supported in the TOP and BOTTOM IO banks.

Further explanation:
The component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
DIFFMTB was chosen because the IO contains symbols and/or properties
consistent with differential master usage and a IOSTANDARD=LVDS_33 property.
Please double check that the types of logic elements and all of their
relevant properties and configuration options are compatible with the
physical site type of the constraint.
-----------------------------------------------------------------------------


The PCI Board Vendor claims in his manual, that these pins are suited for usage as a diff pair.
The Xilinx Datasheets do not say anything against this, IMHO.
The Xilinx mapping tool seems to have a different opinion:)

What am I doing wrong? Would a DIFFMLR be more suited for Banks 1 and 3?


Lost Regards
Tobias


p.s:

from UCF File:
--------------
NET "dig_io[30]" IOSTANDARD = LVDS_33;
NET "dig_io[30]" LOC = K23;
NET "dig_io[31]" IOSTANDARD = LVDS_33;
NET "dig_io[31]" LOC = K22;


from top level file:
--------------------
buf_o_pxlclk: obufds port map (i => o_pxl_clk, o=> dig_io(30), ob => dig_io(31) );
 
On Mar 21, 7:58 am, Tobias Kahre <tobias.ka...@epb-
dienstleistungen.de> wrote:
On a PCI Card I got a XC3SD1800A-4FGG676C.
While trying to establish a differential output pair on Pins K23,K22, i got the following message:

---------------------------------------------------------------------------­-
ERROR:pack:1107 - Pack was unable to combine the symbols listed below into a
   single DIFFMTB component because the site type selected is not compatible.
   The root cause of failure is that the IOSTANDARD=LVDS_33 property is only
   supported in the TOP and BOTTOM IO banks.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   DIFFMTB was chosen because the IO contains symbols and/or properties
   consistent with differential master usage and a IOSTANDARD=LVDS_33 property.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.
---------------------------------------------------------------------------­--

The PCI Board Vendor claims in his manual, that these pins are suited for usage as a diff pair.
The Xilinx Datasheets do not say anything against this, IMHO.
The Xilinx mapping tool seems to have a different opinion:)

What am I doing wrong? Would a DIFFMLR be more suited for Banks 1 and 3?

Lost Regards
Tobias

p.s:

from UCF File:
--------------
NET "dig_io[30]" IOSTANDARD = LVDS_33;
NET "dig_io[30]" LOC = K23;
NET "dig_io[31]" IOSTANDARD = LVDS_33;
NET "dig_io[31]" LOC = K22;

from top level file:
--------------------
buf_o_pxlclk: obufds port map (i => o_pxl_clk, o=> dig_io(30), ob => dig_io(31) );
The Spartan-3A DSP data sheet (DS610) includes the available pin
functionality for every pin.

Page 78
K23 - Bank 1 - IO_L46P_1
K22 - Bank 1 - IO_L46N_1

While both of these can be differential they are in Bank 1 which is a
side bank.

Table 12 has this footnote for the LVDS_33 and LVDS_25 IO standards
"These true differential output standards are supported only on FPGA
banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331."

UG331, starting on page 358, describes the differential I/O support
and banking rules. If the text is not clear then Table 10-20
explicitly documents that LVDS_25 and LVDS_33 outputs are only
available in Banks 0 and 2 (top and bottom).

The bottom line is that these two pins can be used for LVDS, but only
for a LVDS input. Since you have assigned an output buffer to these
pins you are getting a DRC error.

Ed McGettigan
--
Xilinx Inc.
 
On Wed, 21 Mar 2012 08:46:01 -0700 (PDT)
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:

On Mar 21, 7:58 am, Tobias Kahre <tobias.ka...@epb-
dienstleistungen.de> wrote:
On a PCI Card I got a XC3SD1800A-4FGG676C.
While trying to establish a differential output pair on Pins K23,K22, i got the following message:

---------------------------------------------------------------------------­-
ERROR:pack:1107 - Pack was unable to combine the symbols listed below into a
   single DIFFMTB component because the site type selected is not compatible.
   The root cause of failure is that the IOSTANDARD=LVDS_33 property is only
   supported in the TOP and BOTTOM IO banks.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   DIFFMTB was chosen because the IO contains symbols and/or properties
   consistent with differential master usage and a IOSTANDARD=LVDS_33 property.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.
---------------------------------------------------------------------------­--

The PCI Board Vendor claims in his manual, that these pins are suited for usage as a diff pair.
The Xilinx Datasheets do not say anything against this, IMHO.
The Xilinx mapping tool seems to have a different opinion:)

What am I doing wrong? Would a DIFFMLR be more suited for Banks 1 and 3?

Lost Regards
Tobias

p.s:

from UCF File:
--------------
NET "dig_io[30]" IOSTANDARD = LVDS_33;
NET "dig_io[30]" LOC = K23;
NET "dig_io[31]" IOSTANDARD = LVDS_33;
NET "dig_io[31]" LOC = K22;

from top level file:
--------------------
buf_o_pxlclk: obufds port map (i => o_pxl_clk, o=> dig_io(30), ob => dig_io(31) );

The Spartan-3A DSP data sheet (DS610) includes the available pin
functionality for every pin.

Page 78
K23 - Bank 1 - IO_L46P_1
K22 - Bank 1 - IO_L46N_1

While both of these can be differential they are in Bank 1 which is a
side bank.

Table 12 has this footnote for the LVDS_33 and LVDS_25 IO standards
"These true differential output standards are supported only on FPGA
banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O
Resources" in UG331."

UG331, starting on page 358, describes the differential I/O support
and banking rules. If the text is not clear then Table 10-20
explicitly documents that LVDS_25 and LVDS_33 outputs are only
available in Banks 0 and 2 (top and bottom).

The bottom line is that these two pins can be used for LVDS, but only
for a LVDS input. Since you have assigned an output buffer to these
pins you are getting a DRC error.

Ed McGettigan
--
Xilinx Inc.

Ed,

thank you for clarification. The documentation is really comprehensive, so sometimes it is difficult for me to catch up with every detail.
Since the hardware is finished, I will try to use DIFF_SSTL3 now.

Tobias
 

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