Spartan 3 DCM problem

[mokhoo]

Dear All,
I am working on project using Xilinx Spartan3 XC3S2000. I have used one DC
and it worked well. However, when I tried to instantiate another one fo
other purpose, errors appeared in the building phase as follows:

ERROR:NgdBuild:604 - logical block 'CLK_1/DCM_inst' with type 'DCM_2
could
not be resolved. A pin name misspelling can cause this, a missing edi
or ngc
file, or the misspelling of a type name. Symbol 'DCM_2' is not supporte
in
target 'spartan3'.

ERROR:NgdBuild:604 - logical block 'CLK_2/DCM_IFCLK' with type 'DCM_1'
could not be resolved. A pin name misspelling can cause this, a missin
edif
or ngc file, or the misspelling of a type name. Symbol 'DCM_1' is not
supported in target 'spartan3'.

Concerning the above problem I have two questions:
1. Why adding another DCM fails?
2. Why adding another DCM affects the first one although they are no
related to each other in the design?

Thanks and best regards,




---------------------------------------
Posted through http://www.FPGARelated.com

 

[Gabor]

On Sep 27, 6:53 am, "mokhoo" <amn257@n_o_s_p_a_m.yahoo.com> wrote:

Dear All,
I am working on project using Xilinx Spartan3 XC3S2000. I have used one DCM
and it worked well. However, when I tried to instantiate another one for
other purpose, errors appeared in the building phase as follows:

ERROR:NgdBuild:604 - logical block 'CLK_1/DCM_inst' with type 'DCM_2'
could
   not be resolved. A pin name misspelling can cause this, a missing edif
or ngc
   file, or the misspelling of a type name. Symbol 'DCM_2' is not supported
in
   target 'spartan3'.

ERROR:NgdBuild:604 - logical block 'CLK_2/DCM_IFCLK' with type 'DCM_1'
   could not be resolved. A pin name misspelling can cause this, a missing
edif
   or ngc file, or the misspelling of a type name. Symbol 'DCM_1' is not
   supported in target 'spartan3'.

Concerning the above problem I have two questions:
1. Why adding another DCM fails?
2. Why adding another DCM affects the first one although they are not
related to each other in the design?

Thanks and best regards,

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

I have seen issues like this in some versions of ISE, but only for
mixed
VHDL / Verilog designs. What I found was that if I instantiated a
primitive
module in both Verilog and VHDL modules within the design, then ISE
would append a number to the primitive name, and then it couldn't find
the
..ngc file because it didn't have the same name as the library
primitive
after appending the number. I believe this has been fixed in more
recent versions of ISE. I think I was working with ISE 8.x at the
time.

My workaround at the time was to synthesize only the VHDL portion of
the
design with one project, turning off IO buffers. Then the Verilog
part
of the design (which in my case was the top level) instantiated the
pre-built VHDL design as a black box using the .ngc file created
from the VHDL project.

In my case the offending primitives were block RAM's and I had another
workaround that used Coregen to make RAM's instead of using the
RAMB_xx primitives.

Regards,
Gabor

 

[Kim Povlsen]

On Mon, 27 Sep 2010 05:53:16 -0500, "mokhoo"
<amn257@n_o_s_p_a_m.yahoo.com> wrote:

Dear All,
I am working on project using Xilinx Spartan3 XC3S2000. I have used one DCM
and it worked well. However, when I tried to instantiate another It lone for
other purpose, errors appeared in the building phase as follows:

ERROR:NgdBuild:604 - logical block 'CLK_1/DCM_inst' with type 'DCM_2'
could
not be resolved. A pin name misspelling can cause this, a missing edif
or ngc
file, or the misspelling of a type name. Symbol 'DCM_2' is not supported
in
target 'spartan3'.

ERROR:NgdBuild:604 - logical block 'CLK_2/DCM_IFCLK' with type 'DCM_1'
could not be resolved. A pin name misspelling can cause this, a missing
edif
or ngc file, or the misspelling of a type name. Symbol 'DCM_1' is not
supported in target 'spartan3'.

Concerning the above problem I have two questions:
1. Why adding another DCM fails?
2. Why adding another DCM affects the first one although they are not
related to each other in the design?

Thanks and best regards,




---------------------------------------
Posted through http://www.FPGARelated.com

Hi,

It looks like you have been using the Xilinx Core Generator in order
to instantiate the DCM?

If this is the case, a black-box .ngc file for the DCM will be
generated by the tool, and you will have to add a macro search path
pointing to this .ngc file. You can do this from the
translate-options, if you are using ISE.
If not, you can use the "-bd <search-path>" option.

Regards, Kim