Spartan 3 Block RAMs

[mindenpilot]

I have a design where I need to buffer 32 channels of data.
I have to cross clock domains, so I am using asynchronous FIFOs.
I used the core generator to design my FIFO. It is 32 bits wide and 15
entries deep.

I then generate 32 of these FIFOs, but I found I am exceeding the number of
block RAMs available.
The device I am using (or at least considering using) has 24 block RAMs.
The design used 32 (I presume one for each FIFO).

I noticed that the number of actual RAM bits required, ~32K, is much less
than what is available, ~400K.
Is there an easy way to better utilize the block RAMs?

Right now, I am considering three options:
1. using a larger device
2. implementing the FIFOs myself (assuming I have the necessary LUTs).
3. modifying the design so that the 32 channels interleave the data into the
same FIFO. This requires that I read and write it more quickly.

If I had to go with one of these options, I'd prefer either the first or the
last.
Since I am relatively inexperienced, I'd like to implement an elegant
design, and I want to make sure I'm not brute-forcing it.
Your thoughts are appreciated.

Regards,

Adam

 

[sjulhes]

Yes each FIFO will use a block RAM.
You can try to implement your FIFOs using the distributed RAM instaed of the
bloc RAM, it will consume logic element but you shoulr get your 32 FIFO, it
will depend on the size of your FPGA.


"mindenpilot" <weissfamily97@charter.net> a écrit dans le message de news:
Hh8jf.12563$Mj.11084@fe04.lga...

I have a design where I need to buffer 32 channels of data.
I have to cross clock domains, so I am using asynchronous FIFOs.
I used the core generator to design my FIFO. It is 32 bits wide and 15
entries deep.

I then generate 32 of these FIFOs, but I found I am exceeding the number
of
block RAMs available.
The device I am using (or at least considering using) has 24 block RAMs.
The design used 32 (I presume one for each FIFO).

I noticed that the number of actual RAM bits required, ~32K, is much less
than what is available, ~400K.
Is there an easy way to better utilize the block RAMs?

Right now, I am considering three options:
1. using a larger device
2. implementing the FIFOs myself (assuming I have the necessary LUTs).
3. modifying the design so that the 32 channels interleave the data into
the
same FIFO. This requires that I read and write it more quickly.

If I had to go with one of these options, I'd prefer either the first or
the
last.
Since I am relatively inexperienced, I'd like to implement an elegant
design, and I want to make sure I'm not brute-forcing it.
Your thoughts are appreciated.

Regards,

Adam

 

[NOSPAM, Eric]

A good answer would depend on the system frequency you use.
If your FPGA is fast enough to interleave the data, then I would
implement your 3rd proposal. I think that it makes the most efficient
use of the FPGA ressources.

1. is a waste of $
2. I guess that you mean w/ distributed RAMs. I think that you'll
consume a lot of cells for a limited added-value (again, providing that
your datarate actually allow interleaving)

--
Eric DELAGE, Senior ASIC/FPGA Architect
EMail: nospam DOT eric AT gmail DOT com
Homepage: http://eric-delage.no-ip.info

--
"Great discoveries and improvements invariably involve the cooperation
of many minds."
BELL, Alexander Graham (1847-1922)

 

[mindenpilot]

Well, it turns out that using distributed RAM puts me over 100% slice
utilization.
It also turns out that I don't have the bandwidth to interleave.
So, it looks like I'll be looking for a bigger device.
It's a good thing we have disgustingly high margins on these boards!

Thanks and regards,

Adam


"mindenpilot" <weissfamily97@charter.net> wrote in message
news:Hh8jf.12563$Mj.11084@fe04.lga...

I have a design where I need to buffer 32 channels of data.
I have to cross clock domains, so I am using asynchronous FIFOs.
I used the core generator to design my FIFO. It is 32 bits wide and 15
entries deep.

I then generate 32 of these FIFOs, but I found I am exceeding the number
of block RAMs available.
The device I am using (or at least considering using) has 24 block RAMs.
The design used 32 (I presume one for each FIFO).

I noticed that the number of actual RAM bits required, ~32K, is much less
than what is available, ~400K.
Is there an easy way to better utilize the block RAMs?

Right now, I am considering three options:
1. using a larger device
2. implementing the FIFOs myself (assuming I have the necessary LUTs).
3. modifying the design so that the 32 channels interleave the data into
the same FIFO. This requires that I read and write it more quickly.

If I had to go with one of these options, I'd prefer either the first or
the last.
Since I am relatively inexperienced, I'd like to implement an elegant
design, and I want to make sure I'm not brute-forcing it.
Your thoughts are appreciated.

Regards,

Adam

 

[aaaaaa]

Hi Alls,
I think the best way to use the RAM as FIFO is....
1. Use the RAM with pointers a.
2. Increament and decreament of these pointers can be done in logic.
I think it helps .
Regards