Spartan 2e implementation

[jose]

Hi,

I m new in FPGA.
I m sure that someone has for me an answer to my issue. I work with
XC2S300 of the Spartan Familly. when I implement I get the following
warning message:

Warning: NgdBuild: 477 - clock net 'clk_bufgp has non clock
connections. These
problematic connections include pin i1 on block u1_io with type LUT2
...

I try to do gating clock.

What I can do?

 

[Peter Alfke]

Don't do it.
Clock gating is an ugly and error-prone design methodology.
In 99% of all cases there are better ways to design.
What are yiou really trying to do?
Peter Alfke
======
jose wrote:

I try to do gating clock.

What I can do?

 

[Jim English]

Peter Alfke <peter@xilinx.com> wrote in message news:<3F7885B8.D724DC73@xilinx.com>...

Don't do it.
Clock gating is an ugly and error-prone design methodology.
In 99% of all cases there are better ways to design.
What are yiou really trying to do?
Peter Alfke
======
jose wrote:
I try to do gating clock.

What I can do?

OK in general; Clock gating sucks, don't do it.

In specific; An asic I was involved with had a clock gating circuit (I
call them precision kluges). To test the design in the fpga I just
ran the gated clock out of the chip, then back on using a dedicated
global clock buffer. This worked great, and the fitter didn't
complain either.

je