Spartan 2e implementation

[jose]

Hi,

I m new in FPGA.
I m sure that someone has for me an answer to my issue. I work with
XC2S300 of the Spartan Familly. when I implement I get the following
warning message:

Warning: NgdBuild: 477 - clock net 'clk_bufgp has non clock
connections. These
problematic connections include pin i1 on block u1_io with type LUT2
...

I try to do gating clock.

What I can do?

 

[Uwe Bonnes]

jose <jyab2@yahoo.com> wrote:
: Hi,

: I m new in FPGA.
: I m sure that someone has for me an answer to my issue. I work with
: XC2S300 of the Spartan Familly. when I implement I get the following
: warning message:

: Warning: NgdBuild: 477 - clock net 'clk_bufgp has non clock
: connections. These
: problematic connections include pin i1 on block u1_io with type LUT2
: ..

: I try to do gating clock.

First rule: Don't use gated clocks, use the CE input instead.

: What I can do?

Second it looks like you bring in a signal through a clock input, but don't
use it as clock, e.g. you use the input clock as input to a logic gate and
you feed the output of that gate to the clock network.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
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