SOS! What can I do if Synopsys does not allow my statement?

[walala]

Dear all,

I am facing with a problem: Synopsys Design compiler does not allow my
statement for synthesis:


Please save me! Thank you,

-Wlala


Process(rst, clk, enable)
if rst = '1' then
count <= 0;
--Line 85: elsif clk'event and clk = '1' and INPUTEND = '1' then
...
end if;


-----------------------------------------------

Synopsys Error Log:

Error: Enabling expression not permitted outside wait statements on
line 85 (VHDL-2251)
Error: Enabling expression not permitted outside wait statements on
line 85 (VHDL-2251)

---------------------------------------------------------------
v2001.08 Synopsys Inc. 1988-2001. All rights reserved. n-1

messages N. Messages Command Reference

NAME
VHDL-2251 (error) Enabling expression not permitted
outside wait statements %s

DESCRIPTION
This error occurs with statements of the form:
if(clk'event and clock = '1' and enable = '1') then ..
Such expressions are only permitted in: wait until
clk'event and clock = '1' and enable = '1' ... at
present

WHAT NEXT
Modify the if statement with the enabling condition to
conform to suggested style.

n-2 Synopsys Inc. 1988-2001. All rights reserved. v2001.08

 

[steve]

"walala" <mizhael@yahoo.com> wrote in message
news:6f348bd1.0309121303.41f1590c@posting.google.com...

Dear all,

I am facing with a problem: Synopsys Design compiler does not allow my
statement for synthesis:


Please save me! Thank you,

-Wlala


Process(rst, clk, enable)
if rst = '1' then
count <= 0;
--Line 85: elsif clk'event and clk = '1' and INPUTEND = '1' then
...
end if;

Process(rst, clk, enable)
if rst = '1' then
count <= 0;
--Line 85: elsif clk'event and clk = '1' then
if(INPUTEND = '1') then
...
end if;
end if;
? Steve