SOS!Stupid Cadence CDS netlister! What can I do now?

[walala]

Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[Edward J Kalenda]

If you are crashing, you should contact your Field Service AE and have
them look at it. Odds are they will have to give it to R&D who can look
at the core dump. Bitching and moaning here won't get you much of
anything but sympathy, and little of that. We all have our problems with
the software and we learn to deal with them and get on with our work.

On 6 Sep 2003 16:13:25 -0700, mizhael@yahoo.com (walala) wrote:

Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[walala]

Hi, Edward,

You are right... Moaning here may not be useful... I am just writing here in
hoping that somebody else might have the same problem before and knew how to
deal with it...

I have to wait until Monday and contact our university CAD manager then
Cadence guys... I don't know how long I need to wait... before that there is
really nothing I can do other than run the netlister more and more times and
try mu luck...

Is there any direct Cadence support that can help?

Thanks,

-Walala

"Edward J Kalenda" <ed@kalenda.com> wrote in message
news:6rrklvk0inf07sfq1f7hnrvvs349tm7tlf@4ax.com...

If you are crashing, you should contact your Field Service AE and have
them look at it. Odds are they will have to give it to R&D who can look
at the core dump. Bitching and moaning here won't get you much of
anything but sympathy, and little of that. We all have our problems with
the software and we learn to deal with them and get on with our work.

On 6 Sep 2003 16:13:25 -0700, mizhael@yahoo.com (walala) wrote:

Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[cfk]

Dear Walala:
Well, as Gene Wilder said in "Young Frankenstein" "It could be worse, it
could be raining". At least with Cadence (capitalization intentional) you
have an active newsgroup. I know someone who recently spent a fortune for
synopsys (non-capitalization intentional) tools and their answer to
everything is "fill out a trouble ticket on this http web form in the space
1/2inch x 1/2 inch and submit it to the bullpen support group that doesnt
speak english".

Charles

"walala" <mizhael@yahoo.com> wrote in message
news:6f348bd1.0309061513.38604bbb@posting.google.com...

Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[Andrew Beckett]

Walala,

You are using a pretty elderly interface. Not sure if you're using spectreS
or cdsSpice, but either way, these are pretty old and have not really
been updated recently.

If you're using the spectre simulator, you really want to be using the
"spectre" interface (which was introduced in IC443). This is a direct
interface to the spectre simulator which cuts out cdsSpice as the
middle man. There were many reasons for doingi this - particularly
the kind of problems you've seen when dealing with larger circuits.

Artist integrations used to all go via cdsSpice as cdsSpice (whilst
a pretty basic simulator) had a useful front end which allowed
parameterisation of netlists. Now that most modern simulators
are pretty parameterisable, there's no need to go via this route.

If you're hitting the languageSize limits, and you're using spectreS,
then you'll need to set spectreS.init languageSize rather than
cdsSpice.init languageSize.

However, if you can use the "spectre" interface you'll be better
off still.

Regards,

Andrew.

On 6 Sep 2003 16:13:25 -0700, mizhael@yahoo.com (walala) wrote:

Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Erik Wanta]

Michael:
AFAIK cdsSpice is no longer supported by Cadence. Please consider
using spectre instead. Search comp.cad.cadence for Difference between
Spectre or cdsSpice:

Spectre is a newer analog simulation engine than SPICE (cdsSpice is
a heavily worked-over, SPICE2 engine). Spectre has better convergence
strength and way, way better memory management. This means you can
run
more involved, larger simulations for longer time at more precision.
---

Erik

"cfk" <cfk_alter_ego@pacbell.net> wrote in message news:<a8K6b.12144$Gg3.2329@newssvr25.news.prodigy.com>...

Dear Walala:
Well, as Gene Wilder said in "Young Frankenstein" "It could be worse, it
could be raining". At least with Cadence (capitalization intentional) you
have an active newsgroup. I know someone who recently spent a fortune for
synopsys (non-capitalization intentional) tools and their answer to
everything is "fill out a trouble ticket on this http web form in the space
1/2inch x 1/2 inch and submit it to the bullpen support group that doesnt
speak english".

Charles

"walala" <mizhael@yahoo.com> wrote in message
news:6f348bd1.0309061513.38604bbb@posting.google.com...
Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[Edward J Kalenda]

Ah! You're on a University license. Those can be a pain since all
contact with Cadence has to go through some central guy who may not be
all that interested. My son had that problem at Santa Clara University.

Fortunately, there are a number of Cadence employees and customers who
read this group on a regular basis and are very helpful. You probably
have seen Andrew's posing by now.

As a side note, it would be best if you could include actual log output,
with surrounding context, when describing a problem here. Tool version
numbers are also helpful since many problems have already been seen and
fixed. Though getting a newer version installed by your CAD people can
be a hassle at times.

On Sat, 6 Sep 2003 20:04:02 -0500, "walala" <mizhael@yahoo.com> wrote:

Hi, Edward,

You are right... Moaning here may not be useful... I am just writing here in
hoping that somebody else might have the same problem before and knew how to
deal with it...

I have to wait until Monday and contact our university CAD manager then
Cadence guys... I don't know how long I need to wait... before that there is
really nothing I can do other than run the netlister more and more times and
try mu luck...

Is there any direct Cadence support that can help?

Thanks,

-Walala

"Edward J Kalenda" <ed@kalenda.com> wrote in message
news:6rrklvk0inf07sfq1f7hnrvvs349tm7tlf@4ax.com...
If you are crashing, you should contact your Field Service AE and have
them look at it. Odds are they will have to give it to R&D who can look
at the core dump. Bitching and moaning here won't get you much of
anything but sympathy, and little of that. We all have our problems with
the software and we learn to deal with them and get on with our work.

On 6 Sep 2003 16:13:25 -0700, mizhael@yahoo.com (walala) wrote:

Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[Andrew Beckett]

I _hope_ this was a typo ;-)

On Sun, 07 Sep 2003 15:36:50 -0700, Edward J Kalenda <ed@kalenda.com> wrote:

You probably
have seen Andrew's posing by now.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Robert Szczygiel]

walala wrote:

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I had very similiar problems using hspice (via cdsSpice). My solution
for making big netlists (say 50000 elements or more) is very simple:
1. restart Cadence
2. start netlisting
3. ignore all the warnings and errors (even the "time out!" one)
4. cross fingers and be very patient. )

Even when you see the time-out error, the netlist is still being
generated in the background (at least it was in my case).
Just check the final netlist file (for hspice that was hspiceFinal
in the netlist directory).

Having the netlist ready (well, this approach used to work in 99% cases,
suprisingly), I used to give up dfII environment and run the simulator
standalone.

Hope that helps you a bit,

Regards,

Robert

 

[eda support guy]

And once you get a netlist what will you do with it ?
If your netlister is already eating all the core and having a hard time,
do you think you ll be able to even get the simulator to read-in that
circuit ? If you re using sockets netlisting, it is maybe for a
simulator like eldo or hspice. You could better give more details about
what you re trying to do, rather than report only the problem you get.

Whatever this netlist is modelling, I suggest you try another,
compacter, model for it.

Apart from that, I join the others in suggesting you use spectre-direct
or AMS simulator. You might also consider using ultrasim.

walala wrote:

Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[Andrew Beckett]

One good thing is that hspiceD (a "direct" netlisting replacement for hspiceS)
is coming in the IC5033 point release. This does away with cdsSpice (hurrah!)

Andrew.

On Mon, 8 Sep 2003 07:22:31 +0000 (UTC), Robert Szczygiel <RobTM@fake.addr.ess>
wrote:

walala wrote:
And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I had very similiar problems using hspice (via cdsSpice). My solution
for making big netlists (say 50000 elements or more) is very simple:
1. restart Cadence
2. start netlisting
3. ignore all the warnings and errors (even the "time out!" one)
4. cross fingers and be very patient. )

Even when you see the time-out error, the netlist is still being
generated in the background (at least it was in my case).
Just check the final netlist file (for hspice that was hspiceFinal
in the netlist directory).

Having the netlist ready (well, this approach used to work in 99% cases,
suprisingly), I used to give up dfII environment and run the simulator
standalone.

Hope that helps you a bit,

Regards,

Robert

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Erik Wanta]

You mention the use of ultraSim. I thought it was still in beta. I
don't see the ultrasim binary in by Cadence installation
(5.0.32.500.2). I see ultrasim documentation and ultraSim views, but
no binary. ultraSim doesn't show up as a simulator in artist either.
---
Erik

eda support guy <cad_support_at_catena_dot_the_netherlands> wrote in message news:<3f5c7d9f@shknews01>...

And once you get a netlist what will you do with it ?
If your netlister is already eating all the core and having a hard time,
do you think you ll be able to even get the simulator to read-in that
circuit ? If you re using sockets netlisting, it is maybe for a
simulator like eldo or hspice. You could better give more details about
what you re trying to do, rather than report only the problem you get.

Whatever this netlist is modelling, I suggest you try another,
compacter, model for it.

Apart from that, I join the others in suggesting you use spectre-direct
or AMS simulator. You might also consider using ultrasim.

walala wrote:
Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

 

[Andrew Beckett]

Erik,

UltraSim (the simulator part) is not (currently) in the IC stream. It's a
separate stream, USIM31 (released March 27 2003) or USIM32 (released July 11
2003). It may end up being rolled into the IC stream at some point once things
have settled down after the acquisition (I'm not really sure if this is
planned), but certainly for now it is in a separate stream.

Regards,

Andrew.

On 8 Sep 2003 15:10:25 -0700, erikwanta@starband.net (Erik Wanta) wrote:

You mention the use of ultraSim. I thought it was still in beta. I
don't see the ultrasim binary in by Cadence installation
(5.0.32.500.2). I see ultrasim documentation and ultraSim views, but
no binary. ultraSim doesn't show up as a simulator in artist either.
---
Erik

eda support guy <cad_support_at_catena_dot_the_netherlands> wrote in message news:<3f5c7d9f@shknews01>...
And once you get a netlist what will you do with it ?
If your netlister is already eating all the core and having a hard time,
do you think you ll be able to even get the simulator to read-in that
circuit ? If you re using sockets netlisting, it is maybe for a
simulator like eldo or hspice. You could better give more details about
what you re trying to do, rather than report only the problem you get.

Whatever this netlist is modelling, I suggest you try another,
compacter, model for it.

Apart from that, I join the others in suggesting you use spectre-direct
or AMS simulator. You might also consider using ultrasim.

walala wrote:
Dear all,

I don't know what the hell is the Cadence software... esp. the CDS
netlister in the Affirma Analog environment...

After running "Create Final Netlist" for one night, it poped up an
error message saying "running out of memory", ...

Ooops, I searched the document, and managed to increase
"cdsSpice.init" "language size" to a larger size,...

After running "Create Final Netlist" for one more night, it popped up
an error massage saying "segment violation", "core dumped", ...

And after running "Create Final Netlist" for one more night, it popped
up an error message saying "waiting for final netlist", "waiting...",
"waiting"..."waiting for final netlist", then suddenly, "time out!
could not create final netlist..." (before that, everything seems
successful from the icfb log window...)

I cannot help to ask did the Cadence guys learn "userfriendly design"
in their computer science classes?

I spend every day search documents, reading faqs, hoping to solve the
problem, and spend every night running the program, but now one week
past, I got nothing out...

What can I do now? Can anybody help me out of this swamp?

Thanks a lot,

-Walala

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[John Gianni]

erikwanta@starband.net (Erik Wanta) wrote in message news:<84018314.0309081410.54962e58@posting.google.com>...

You mention the use of ultraSim. I thought it was still in beta.

1. Nah ... UltraSim has been released for a few months now.

2. We've been using it in the documented Cadence AMS flow for six months
at least; and it's being demo'd & tutorial'd at the upcoming Cadence
(International Users Group www.cadenceusers.org) this very week
(Sunday September 14th to September 17th).

3. I'll send, to your company address, a generic step-by-step walk-thru
that your grandmother could follow, taking a design thru UltraSim,
Spectre, and other simulators which is also being piloted (as we speak)
by your same company at another site in the midwest.

--
All my USENET posts are personal opinion for Cadence users' benefit;
absolutely none are company sanctioned statements on company time.