Sonata error:Help

[VHDL User]

Hi All,
I wrote the following code as a part of a larger design.The procedure is
basically to add 2 -Width- bit vectors which are in twos complement
representation.I used a generic b-bit adder for this purpose.
My problem is that Sonata on compilation gives the following error(s):
-----------Sonata Error-----------
Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3,
Build#9.
Copyright(C) Symphony EDA 1997-2004. All rights reserved.
Reading /usr/local/Simili23/bin/symphony.ini ...
Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly)
Library 'workspace' ==> workspace.sym
Library 'work' ==> Library 'workspace' ==> workspace.sym
Reading $SYMPHONYEDA/lib/ieee/ieee.sym/std_logic_1164/prim.var
Reading workspace.sym/types/prim.var
Parsing Entity:stage @ line stage.vhd:6
Writing workspace.sym/stage/prim.var
Parsing Architecture:stage(archstage) @ line stage.vhd:16
Reading workspace.sym/adder/prim.var
Error: CSVHDL0002: stage.vhd: (line 54): Syntax error near 'generic',
expecting `''
Error: CSVHDL0002: stage.vhd: (line 54): Invalid prefix for an
indexed/selected/slice/attribute name
Error: CSVHDL0002: stage.vhd: (line 54): Invalid prefix for an
indexed/selected/slice/attribute name
Error: CSVHDL0002: stage.vhd: (line 54): Invalid prefix for an
indexed/selected/slice/attribute name
----------------------------
I have included the procedure below.The adder compiles cleanly;it is only
the instantiation (line54) giving errors.
----------------The Code--------------

procedure add( signal A,B:in std_logic_vector(0 to Width-1);signal
sumut std_logic_vector(0 to Width-1)) is --A+B
begin
if ((A(Width-1)='0') and (B(Width-1)='0')) then --both
positive
sum(Width-1)<='0';
--line54: adder1:adder generic map (bitsize=>Width-1) port
map (X=>A(0 to Width-2),Y=>B(0 to Width-2),Ci=>zero,S=>temp(0 to
Width-2),Co=>car) ;
if(car='0') then
sum(0 to Width-2)<=temp;
ovf<=false;
else
ovf<=true;
end if;
--.....and rest of code
----------------------------------------
I want to know if the instantiation inside the procedure is right,and the
reasons and solution(s) for compile error.
Thanks a lot.

 

[Mike Treseler]

VHDL User wrote:

My problem is that Sonata on compilation gives the following error(s):
Error: CSVHDL0002: stage.vhd: (line 54): Syntax error near 'generic',
expecting `''

I want to know if the instantiation inside the procedure is right

No.
A procedure can contain only sequential statements.
An instance is a process, and must be in architecture scope.

-- Mike Treseler