some VHDL error

[Santosh]

Hi,
I know this is a dumb question, asking to decode some error directly.
I got the following error,

" Aggregate expression cannot be scalar type
ieee.std_logic_1164.std_logic"

and the code is

"parrout(7 downto 0) => dataout_2(7 downto 0),".

 

[maurizio.tranchero]

On Dec 26, 7:33 am, Santosh <santos...@gmail.com> wrote:

Hi,
 I know this is a dumb question, asking to decode some error directly.
 I got the following error,

" Aggregate expression cannot be scalar type
ieee.std_logic_1164.std_logic"

and the code is

"parrout(7 downto 0)   =>   dataout_2(7 downto 0),".

Hi Santosh,

First: when you provide a sample of code, please do include also the
signal definition.

Second: when reporting an error tell us also the compiler you are
using.

Third: some compilers do not allow the usage of ranges on left and
right operands during
assignments. If parrout is defined as 7 downto 0, you can try with
defining a simple signal
called dataout_2_7dt0 and write two separate assignments:

dataout_2_7dt0 <= dataout_2(7 downto 0);
....
parrout(7 downto 0) => dataout_2_7dt0,

In case parrout is not only 7 downto 0, but wider, you should use a
temporary signal

signal temp_parrout : std_logic_vector( N-1 downto 0 ); -- with N= the
actual width of parrout

temp_parrout <= "00000000" & dataout_2(7 downto 0); -- with "00000000"
of the right dimension

parrout => temp_parrout,

Good luck.
Maurizio

 

[Santosh]

Hey
Maurizio,

I am sorry for incomplete question but thanks for your help I got the
clue.


Regards
Santosh.

 

[maurizio.tranchero]

I am sorry for incomplete question but thanks for your help I got the
clue.

Great! You're welcome.

Happy new year!
Maurizio