some vector to bit constructs

[TestUser13]

Hi,

How defined the working the ~, & operators in this context?
It seems ~a is ~a[0] but I'm not sure also what does &a ?

module test(u, v);
input u;
output v;

reg c, d;
reg [3:0] a;

initial
begin
a = 3'b000;
c = &a;
c = ~a;
d = 0;
end
endmodule

 

[Gabor Szakacs]

On 2/7/2016 5:24 AM, TestUser13 wrote:

Hi,

How defined the working the ~, & operators in this context?
It seems ~a is ~a[0] but I'm not sure also what does &a ?

module test(u, v);
input u;
output v;

reg c, d;
reg [3:0] a;

initial
begin
a = 3'b000;
c = &a;
c = ~a;
d = 0;
end
endmodule

~ is the bitwise inversion operator. "~a" is a vector of the same
length as "a" where each bit is inverted from the same bit in "a".
You can also call this the 1's complement of "a".

Then when you make an assignment of "~a" (4 bits in your case) to
a scalar reg "c" Verilog by default gives you only the rightmost
bit(s) required to fill the left side of the equation. So in
effect c will be bit 0 of the inverted vector, which for this
case is the same as the inversion of bit 0 of the original vector.

When you use "&" or similar operators as a unary operator, it becomes
a "reduction" operator. This means to use the operator on all bits
of the vector. So in the case of "&a" it means:
a[3] & a[2] & a[1] & a[0]

similarly "^a" would be the exclusive OR of all bits of "a", etc.

--
Gabor