Some help with Warp VHDL code

T

The6502Man

Guest
Sorry for this being a long post, but I have a problem. I'm using Warp 6.3,
and I need a Cypress 37032 or 64 44 pin device to act as multiple latches to
replace '573As. My issues are space, not cost. I have written this, but
upon compilation, it generates errors during the fitting process:

Error: Logic equation for signal adr0(7).LH[30] is redefining a banked
expression.
Error: Logic equation for signal adr0(6).LH[31] is redefining a banked
expression.
Error: Logic equation for signal adr0(5).LH[32] is redefining a banked
expression.
Error: Logic equation for signal adr0(4).LH[33] is redefining a banked
expression.
Error: Logic equation for signal adr0(3).LH[34] is redefining a banked
expression.
Error: Logic equation for signal adr0(2).LH[35] is redefining a banked
expression.
Error: Logic equation for signal adr0(1).LH[36] is redefining a banked
expression.
Error: Logic equation for signal adr0(0).LH[37] is redefining a banked
expression.


I've looked all over, and can't find any references to a banked expression.
I assume it is an error with trying to route the busses, but I would have
thought it would give me a simple 'cannot route equation' or something.



Here's the code:


Library ieee;
use ieee.std_logic_1164.all;

entity decode is port(
datain: in std_logic_vector(7 downto 0); --address A8-A15
adr0: out std_logic_vector(7 downto 0); --address A8-A15
adr1: out std_logic_vector(7 downto 0); --address A8-A15
adr2: out std_logic_vector(3 downto 0); --address A8-A15

A0, A1, Latch: in std_logic);

attribute pin_numbers of decode:entity is "datain(0):40 datain(1):41
datain(2):42 "
& "datain(3):43 datain(4):44 datain(5):1 "
& "datain(6):2 datain(7):3 "
& "adr0(0):37 adr0(1):36 adr0(2):35 "
& "adr0(3):34 adr0(4):33 adr0(5):32 "
& "adr0(6):31 adr0(7):30 "
& "adr1(0):25 adr1(1):24 adr1(2):23 "
& "adr1(3):22 adr1(4):21 adr1(5):20 "
& "adr1(6):19 adr1(7):18 "
& "adr2(0):15 adr2(1):14 adr2(2):13 "
& "adr2(3):12 "
& "A0:4 A1:7 Latch:27";

end decode;


architecture mem_decode of decode is
begin
mapper: process (datain, A0, A1, Latch)
begin

if (Latch ='0') AND (A0 = '0') AND (A1 = '0')then
adr0 <= datain;
end if;
if (Latch ='0') AND (A0 = '1') AND (A1 = '0')then
adr1 <= datain;
end if;
if (Latch ='0') AND (A0 = '0') AND (A1 = '1')then
adr2(0) <= datain(0);
adr2(1) <= datain(1);
adr2(2) <= datain(2);
adr2(3) <= datain(3);
end if;

end process;
end mem_decode;




Any help would be greatly appreciated!!


Tony
 
Try fitting into the 37064 device...

Clyde

"The6502Man" <needonebad9@yahoo.com> wrote in message news:<JG6tb.146053$mZ5.999655@attbi_s54>...
Sorry for this being a long post, but I have a problem. I'm using Warp 6.3,
and I need a Cypress 37032 or 64 44 pin device to act as multiple latches to
replace '573As. My issues are space, not cost. I have written this, but
upon compilation, it generates errors during the fitting process:

Error: Logic equation for signal adr0(7).LH[30] is redefining a banked
expression.
Error: Logic equation for signal adr0(6).LH[31] is redefining a banked
expression.
Error: Logic equation for signal adr0(5).LH[32] is redefining a banked
expression.
Error: Logic equation for signal adr0(4).LH[33] is redefining a banked
expression.
Error: Logic equation for signal adr0(3).LH[34] is redefining a banked
expression.
Error: Logic equation for signal adr0(2).LH[35] is redefining a banked
expression.
Error: Logic equation for signal adr0(1).LH[36] is redefining a banked
expression.
Error: Logic equation for signal adr0(0).LH[37] is redefining a banked
expression.


I've looked all over, and can't find any references to a banked expression.
I assume it is an error with trying to route the busses, but I would have
thought it would give me a simple 'cannot route equation' or something.



Here's the code:


Library ieee;
use ieee.std_logic_1164.all;

entity decode is port(
datain: in std_logic_vector(7 downto 0); --address A8-A15
adr0: out std_logic_vector(7 downto 0); --address A8-A15
adr1: out std_logic_vector(7 downto 0); --address A8-A15
adr2: out std_logic_vector(3 downto 0); --address A8-A15

A0, A1, Latch: in std_logic);

attribute pin_numbers of decode:entity is "datain(0):40 datain(1):41
datain(2):42 "
& "datain(3):43 datain(4):44 datain(5):1 "
& "datain(6):2 datain(7):3 "
& "adr0(0):37 adr0(1):36 adr0(2):35 "
& "adr0(3):34 adr0(4):33 adr0(5):32 "
& "adr0(6):31 adr0(7):30 "
& "adr1(0):25 adr1(1):24 adr1(2):23 "
& "adr1(3):22 adr1(4):21 adr1(5):20 "
& "adr1(6):19 adr1(7):18 "
& "adr2(0):15 adr2(1):14 adr2(2):13 "
& "adr2(3):12 "
& "A0:4 A1:7 Latch:27";

end decode;


architecture mem_decode of decode is
begin
mapper: process (datain, A0, A1, Latch)
begin

if (Latch ='0') AND (A0 = '0') AND (A1 = '0')then
adr0 <= datain;
end if;
if (Latch ='0') AND (A0 = '1') AND (A1 = '0')then
adr1 <= datain;
end if;
if (Latch ='0') AND (A0 = '0') AND (A1 = '1')then
adr2(0) <= datain(0);
adr2(1) <= datain(1);
adr2(2) <= datain(2);
adr2(3) <= datain(3);
end if;

end process;
end mem_decode;




Any help would be greatly appreciated!!


Tony
Click to expand...
 
The6502Man wrote:
Sorry for this being a long post, but I have a problem. I'm using Warp 6.3,
and I need a Cypress 37032 or 64 44 pin device to act as multiple latches to
replace '573As. My issues are space, not cost. I have written this, but
upon compilation, it generates errors during the fitting process:
Click to expand...
Consider inferring registers instead of latches.

-- Mike Treseler
 
Thanks Clyde. After I posted this thats what i thought. Chose the 37064
and it compiled and fitted without a problem.



Tony

<clydes@theworld.com> wrote in message
news:dbe48672.0311141148.ffa9d9a@posting.google.com...
Try fitting into the 37064 device...

Clyde
Click to expand...
 
In article <JG6tb.146053$mZ5.999655@attbi_s54>,
The6502Man <needonebad9@yahoo.com> wrote:
[....]
is redefining a banked
expression.
Click to expand...
This is a known bug in the Cypress tool kit. If you can make edge
operated flip-flops, do the job, it is best to go with them. If not, you
have to come up with some way to fool the tools into not optimizing the
signals into a "bank". I managed to do it but it was buy randomly
changing the code around until it worked.

--
--
kensmith@rahul.net forging knowledge
 
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