Some error of layout presented by Assura

[Adam]

Hi Friends,

I got some error when doing DRC using Assura:

Rule No. 815 : GRLUP09b: Ratio (RX substrate contact)/(NFET gate
not over N3) >= 0.007.

I am not sure what this message means. Would you please give me
some hint?

Thanks,
Adam

 

[The Master]

On Wed, 29 Oct 2008, Adam wrote:

Rule No. 815 : GRLUP09b: Ratio (RX substrate contact)/(NFET gate
not over N3) >= 0.007.

I am not sure what this message means. Would you please give me
some hint?

Without a copy of the design rules, or the Assura DRC rules file, I don't
have the foggiest idea. However, the wording sounds like it might be
saying you don't have enough substrate contacts... Try adding some, and
see what happens.

 

[Riad KACED]

Hi Adam,

Your question is rather technology dependent and it is very hard for
those how don't know your process/PDK, like me for example, to give
any helpful advise. I'm for example wondering what is RX and N3. That
would be more helpful if you give more details about your case.
Anyway. The fair answer to you question is to go back to your Design
Rule Manual that your foundry provides you. The DRC deck is actually a
pure translation of the manufacturing data, available from your DRM,
into a given syntax/language that is compiled by your DRC engine like
Assura, Calibre ...
Well, as far as I understand, your rule is looking for a minimum ratio
between a substrate contact and FET gate which should be >= 0.7%. This
sounds like a antenna rule. Basically, you need to connect the gate of
your FET into an antenna diode. An antenna diode is as simple as a
substrate contact that makes a PN junction. You need to connect this
diode into your gate using the lowest metal level, i.e METAL1 in most
process. To summarize, this diode will act as antenna that protects
the thin oxide of your gate during the processing of your chip. One
minimum contact is usually enough to fulfil this rule, assuming
reasonable FET sizes of course.

Again, give a look at your DRM, that's the best location to find the
right explanation

Regards,
Riad.

 

[Adam]

On Oct 29, 6:29 pm, Riad KACED <riad.ka...@gmail.com> wrote:

Hi Adam,

Your question is rather technology dependent and it is very hard for
those how don't know your process/PDK, like me for example, to give
any helpful advise. I'm for example wondering what is RX and N3. That
would be more helpful if you give more details about your case.
Anyway. The fair answer to you question is to go back to your Design
Rule Manual that your foundry provides you. The DRC deck is actually a
pure translation of the manufacturing data, available from your DRM,
into a given syntax/language that is compiled by your DRC engine like
Assura, Calibre ...
Well, as far as I understand, your rule is looking for a minimum ratio
between a substrate contact and FET gate which should be >= 0.7%. This
sounds like a antenna rule. Basically, you need to connect the gate of
your FET into an antenna diode. An antenna diode is as simple as a
substrate contact that makes a PN junction. You need to connect this
diode into your gate using the lowest metal level, i.e METAL1 in most
process. To summarize, this diode will act as antenna that protects
the thin oxide of your gate during the processing of your chip. One
minimum contact is usually enough to fulfil this rule, assuming
reasonable FET sizes of course.

Again, give a look at your DRM, that's the best location to find the
right explanation

Regards,
Riad.

Hi Riad,

Thank yo so much for your detailed answer.

I have read the manual of the design kit and and related help
information, and I found out that this is some error related to latch
up. As far as I know, all the active components need a guard ring to
reduce latch up. Are there any other method which has to be used in
order to eliminate latch up? Since there is still similar errors even
when guard rings are added.

Thanks,
Adam

 

On Oct 29, 3:29 pm, Riad KACED <riad.ka...@gmail.com> wrote:

Hi Adam,

Your question is rather technology dependent and it is very hard for
those how don't know your process/PDK, like me for example, to give
any helpful advise. I'm for example wondering what is RX and N3.

Riad,

FYI.

The "GR" prefix and the layer names mean this is an IBM process
(the deck could come from one of their partners, Chartered,
Samsung, etc., but really from IBM).

RX is diffusion, TSMC equiv is OD.

N3 is a triple-well definition layer. TSMC equiv is DNW
(not exactly, but close enough for this discussion).

The check is saying that not only do you have to satisfy the
raw substrate/well tap density rule (usually something like
all S/D diff must have a sub/well tap within 10um), but
that you can't get away with just a tiny little minimum spot
size tap, it has to a reasonable size (in this case, based
on gate area for reasons not obvious to me).

-Jay-
diff must have

 

[Adam]

On Nov 12, 3:14 pm, jayl-n...@accelerant.net wrote:

On Oct 29, 3:29 pm, Riad KACED <riad.ka...@gmail.com> wrote:

Hi Adam,

Your question is rather technology dependent and it is very hard for
those how don't know your process/PDK, like me for example, to give
any helpful advise. I'm for example wondering what is RX and N3.

Riad,

FYI.

The "GR" prefix and the layer names mean this is an IBM process
(the deck could come from one of their partners, Chartered,
Samsung, etc., but really from IBM).

RX is diffusion, TSMC equiv is OD.

N3 is a triple-well definition layer. TSMC equiv is DNW
(not exactly, but close enough for this discussion).

The check is saying that not only do you have to satisfy the
raw substrate/well tap density rule (usually something like
all S/D diff must have a sub/well tap within 10um), but
that you can't get away with just a tiny little minimum spot
size tap, it has to a reasonable size (in this case, based
on gate area for reasons not obvious to me).

-Jay-
diff must have

Hi Jay,

Thanks for your reply.

Yes, it is IBM process. After adding guard rings to all active
components(I didn't add guard rings to varactors before), this error
has been eliminated.
There is another similar error which is "GRLUP09bTW: Ratio (RX
TripleWell contact)/(NFET gate not over N3) >= 0.004." This error
occurs to all the active components even when
there are guard rings. Do you have any idea what can be done to
eliminate this error?

Thanks.

Regards,
Adam

 

On Nov 12, 12:54 pm, Adam <wang.adam2...@gmail.com> wrote:

Yes, it is IBM process. After adding guard rings to all active
components(I didn't add guard rings to varactors before), this error
has been eliminated.
There is another similar error which is "GRLUP09bTW: Ratio (RX
TripleWell contact)/(NFET gate not over N3) >= 0.004." This error
occurs to all the active components even when
there are guard rings. Do you have any idea what can be done to
eliminate this error?

More substrate taps and/or bigger substrate taps, within the T3 you've
drawn your transistors in.

The rule goes something like this:

Every time I see any nfet gates inside T3, I'm going to draw a NxN
micron
square. For all the T3 inside that square, I'm going to calculate:

(total substrate tap area)/(total nfet gate area)

If the value is < 0.004, it's an error.

The value N is defined in your design rule manual.

You're saying "even when there are guard rings", but one of
the following must be true:

* The guardring doesn't include substrate tap.

* The substrate tap in the guardring is outside your T3,
so doesn't do any good.

* The guardring is surrounding a big area, with a lot of large-area
gates inside, and you don't have substrate taps inside the
guardring.

-Jay-

 

[Adam]

On Nov 13, 7:03 pm, jayl-n...@accelerant.net wrote:

On Nov 12, 12:54 pm, Adam <wang.adam2...@gmail.com> wrote:

Yes, it is IBM process. After adding guard rings to all active
components(I didn't add guard rings to varactors before), this error
has been eliminated.
There is another similar error which is "GRLUP09bTW: Ratio (RX
TripleWell contact)/(NFET gate not over N3) >= 0.004." This error
occurs to all the active components even when
there are guard rings. Do you have any idea what can be done to
eliminate this error?

More substrate taps and/or bigger substrate taps, within the T3 you've
drawn your transistors in.

The rule goes something like this:

Every time I see any nfet gates inside T3, I'm going to draw a NxN
micron
square. For all the T3 inside that square, I'm going to calculate:

(total substrate tap area)/(total nfet gate area)

If the value is < 0.004, it's an error.

The value N is defined in your design rule manual.

You're saying "even when there are guard rings", but one of
the following must be true:

* The guardring doesn't include substrate tap.

* The substrate tap in the guardring is outside your T3,
so doesn't do any good.

* The guardring is surrounding a big area, with a lot of large-area
gates inside, and you don't have substrate taps inside the
guardring.

-Jay-

Hi Jay,

Thank you for your detailed reply.

I am not able to find T3 level in the LSW. I tried to use N3. I got
some result as follows.

If I add RX triple-well contact (using N well, N3, BP , RX and
RX_M1 contact), this error is still there, and there is a new error:

GR268a: [(RX P+ junction maximum distance to (RX NW contact
touching (RX touching CA)
over (NW not over N3))] for preventing latchup <= 20.000um.

What I understand is that the RX triple-well contacts were
recognized as RX P+ junctions.

However, if I delete the NW from this RX triple-well, both errors
are eliminated.

But there comes another error: GR3W05: N3 must be within NW >=
0.900um.

This means the N well should not be deleted.

Do you think if I did something wrong?

Thanks a lot.

Regards,
Adam