software for beginners

[David R Brooks]

FPGA design tools won't synthesis into "gates", but into the FPGA's
basic units. Typically, these are some variant of a tiny ROM followed by
a flipflop.
What gets synthesised is the ROM content plus the interconnect.

cirutech wrote:

Hi everybody,
I am approaching to FPGA design for university, and I will use
Altera's devices.
I have already downloaded Quartus II but now, to begin understand VHDL
syntax, I would like to find a software which allows me to try little
pieces of VHDL code, compile it and see it synthetized in logic gates.

Quartus II seems ok for big projects, but not for learning examples.

anybody has any tip?

thanks since now,

C.
From - Thu

 

[Mike Treseler]

cirutech wrote:

I am approaching to FPGA design for university, and I will use
Altera's devices.
I have already downloaded Quartus II but now, to begin understand VHDL
syntax, I would like to find a software which allows me to try little
pieces of VHDL code, compile it and see it synthetized in logic gates.

Quartus II seems ok for big projects, but not for learning examples.

anybody has any tip?

See the reference design here
http://home.comcast.net/~mike_treseler/

 

[cirutech]

Hi everybody,
I am approaching to FPGA design for university, and I will use
Altera's devices.
I have already downloaded Quartus II but now, to begin understand VHDL
syntax, I would like to find a software which allows me to try little
pieces of VHDL code, compile it and see it synthetized in logic gates.

Quartus II seems ok for big projects, but not for learning examples.

anybody has any tip?

thanks since now,

C.

 

[Tricky]

Im not sure if the licence you have supports it, but try using the RTL
viewer in Quartus (Tools->netlist viewers->RTL view). This should show
you your design in gates and registers. It should also work fine for
small test builds aswell (It will quite happily make a design using
just 1 register and a couple of gates). I like to use it to see how
quartus will synthesize certain bits of VHDL. You dont need to do a
full compile to get to this stage, just run "Start Analysis and
Synthesis", That will give you access to the RTL view, and the
technology map viewer if you're interested to see how it would be
implemented on the FPGA at the Lut/register level.

My advice is just set up a project with a single file that you will
test your code in, and just change it and re-compile it. You may want
to copy and paste the code somewhere else if you want to keep it.

 

[cerocca]

Thanks everybody for the answers.
I think I'll keep working with Quartus II so to optimize also my
learning of this software, even if it's not so easy at the beginning..

all the best,

C

On Feb 21, 1:37 am, Tricky <Trickyh...@gmail.com> wrote:

Im not sure if the licence you have supports it, but try using the RTL
viewer in Quartus (Tools->netlist viewers->RTL view). This should show
you your design in gates and registers. It should also work fine for
small test builds aswell (It will quite happily make a design using
just 1 register and a couple of gates). I like to use it to see how
quartus will synthesize certain bits of VHDL. You dont need to do a
full compile to get to this stage, just run "Start Analysis and
Synthesis", That will give you access to the RTL view, and the
technology map viewer if you're interested to see how it would be
implemented on the FPGA at the Lut/register level.

My advice is just set up a project with a single file that you will
test your code in, and just change it and re-compile it. You may want
to copy and paste the code somewhere else if you want to keep it.