L
luc
Guest
Hi,
In a verilog netlist we don't specify any P/G-pads.
When you do a P&R with SoC Encounter you can read in a IO-placement
file.
How can you create P/G-pads and Corner cells in the IO-placement file
and place them on the certain side of the chip (Corners in the 4
corners of the chip and the created P/G-pads evenly distributed around
the chip).
Luc
In a verilog netlist we don't specify any P/G-pads.
When you do a P&R with SoC Encounter you can read in a IO-placement
file.
How can you create P/G-pads and Corner cells in the IO-placement file
and place them on the certain side of the chip (Corners in the 4
corners of the chip and the created P/G-pads evenly distributed around
the chip).
Luc