soc encounter verilog netlist bug

[Jim]

Hi all,

I used soc encounter to generate the layout and the corresponding
verilog netlist. Then I modified the netlist, and used it as the input
to generated the layout and the verilog netlist again. The new netlist
was of course changed since new wires and buffers were inserted. But
the new netlist is not correct since some old wires are not connected,
and simulation of the new netlist failed. I am wondering if this is a
know bug of encounter, and how to avoid it.

Thanks,
Jim