soc encounter keeps increasing the density

[Jim]

Hi everyone,

I am using soc encounter to place and route my design. The initial
density after place is around 40%, but after performing optDesign or
other operations, the density rise to 80% by resizing cells and
inserting buffers. The timing constraints are fairly met in design
complier (only a little bit violation on several paths, since I
constrain tight), although without wire models. I am wondering if it
is normal in 15nm technology. I don't think it makes sense to increase
the area by so much. I know I can set max_density to prevent it, but i
would like to know if there is any better solution, and if there is
anything wrong.


Thanks,
Jim