SMPS - effects of casing

[TP]

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

 

[PeteS]

You don't say whether this is your design or someone else's, or if the
metal case is grounded.

Whatever those things, the odds-on cause of your problem is poor layout
perhaps with poor design in the loop compensation network.

Switchmode supplies require great attention to layout (and indeed
should be modeled at the layout level if you have the tools) for both
stability and EMI issues.

If you designed the circuit, can you identify the key parameters (Vin
range, Vout, Iout range, Cin, Cout, controller?

Cheers
Pete

TP wrote:

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current
consumption.
I would be interested in the insights and experiences of others in
this area.

 

[Ken Smith]

In article <jol1v0tu76tut5for8kbuq379ft7eemgnv@4ax.com>,
TP <name@usenet.com> wrote:

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

If you use unshielded inductors and place a conductive case in the
inductors magnetice field, you can significantly change the inductance.

If you ground the PCB to the case in more than one place (a common
mistake) the case changes the ground wiring and can run the switching
spikes into the control circuit which can be bad news.

When you place it in the case, you often also change the cabling from the
test set up to the production one. If the loop stability is a bit flaky,
changing the impedance on the input wiring can make for loop oscillation.

When you put the converting into its case, it is running at a different
temperature. If you haven't made sure the circuit will work equally well
over the temperature range, this may be what you are seeing.

Last but not least, you may be wrong and the effect isn't happening at
all. The board in the case is a defective one or something that has lead
you down the garden path.




--
--
kensmith@rahul.net forging knowledge

 

[Joerg]

Hello TP,

The are a few ways to approach this from an experimenter's side to narrow down the neuralgic points:

Hold a piece of the same kind of metal close to the circuit from different sides. About the same distance that the case walls would be. Any changes? For example, when coming close to the magnetics?

Next, do the same but now ground the metal to the PCB with a very short and wide braid. Hoping that there is only one ground, else you'd be in for trouble anyway.

Regards, Joerg

http://www.analogconsultants.com

 

[John Popelish]

TP wrote:

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

What kind of inductors are you using in these supplies? Some shapes
have almost no external field (toroids) and some have extended
external fields (drum cores).

--
John Popelish

 

[Genome]

"TP" <name@usenet.com> wrote in message
news:jol1v0tu76tut5for8kbuq379ft7eemgnv@4ax.com...

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

That sort of behaviour seems strange.

I mean.

I might anticipate problems with EMI external to the design, and work to
exclude/minimize it, but I would be seriously dissapointed if it fucked its
own bucket after incorporation.

Perhaps it's because you are a top posting idiot?

DNA

 

[legg]

On Fri, 21 Jan 2005 22:04:50 -0600, TP <name@usenet.com> wrote:

TP wrote:

I have seen changes in behavior of switchmode power supplies when
installed in a metal case as opposed to out of the case on the bench.
This includes switching instability and increased current consumption.
I would be interested in the insights and experiences of others in
this area.

On Fri, 21 Jan 2005 16:26:08 -0500, John Popelish <jpopelish@rica.net
wrote:

What kind of inductors are you using in these supplies? Some shapes
have almost no external field (toroids) and some have extended
external fields (drum cores).

Thanks to everyone who has reponded.

The inductors are toroids. There are common mode chokes on the input
and the output.

As the unit is slid into the case, the problem begins as the
controller IC enters the case. The problem can be seen on the scope
as irregular switching pulses--one to three maximum duty pulses
followed by one pulse too short to fully switch on the MOSFET.

The compensation loop has been suspected but does not appear to be the
culprit.

You are describing subharmonic oscillation, though. If the error
amplifier is generating the pattern, then it's not handling built-in
delays very well - it normally shouldn't be able to slew the control
signal from maximum to minimum in less than one switching cycle
interval, as this oscillation pattern would require.

We have tried filtering the feedback input and the current sense
input.

The short cycle cannot be noise-induced if power switch conduction has
not occurred to initiate the noise.

If there is some kind of slope compensartion generator present that is
dependant on the gate drive period, it is possible that you are
failing to discharge it properly at full duty cycle. This allows a
multi-stable chaotic condition for the controller.

Buffers or isolators with non-uniform slew rates - ie open collector
or emitter followers with oversized loads - can create the same
chaotic behaviour. This includes opto-couplers and shunt regulator
feedback elements.

The case is grounded at only one point.

Not such a great idea in an isolated converter, as both sides of the
isolation barrier need chassis returns for locally generated common
mode currents. The chassis ties selected should shorten the return
path to the specific noise sources.

The layout is crowded; case fit is tight.

Common mode chassis currents increase as capacity to frame of noisy
nodes increases. Returning these to a relatively noise-voltage-free
plane on the appropriate side of the isolation barrier prevents their
having to cross the isolation barrier from the side that owns the
shortest common-mode filter capacitors current path.

This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

Don't shoot the messenger by trying to blame the chip. It's trying to
tell you something. All you have to do is look closer. Test your
circuit above 75% duty cyle - the behaviour should show up in some
more modest form, without a full chassis - just a plate or partial
form that doesn't interfere with troubleshooting.

RL

 

[John Popelish]

TP wrote:
(snip)

This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

What Linear Technology part number? I would like to look at the data
sheet for clues to what might be causing your problems.

--
John Popelish

 

[TP]

TP wrote:
(snip)
This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

On Sat, 22 Jan 2005 13:14:25 -0500, John Popelish <jpopelish@rica.net>
wrote:

What Linear Technology part number? I would like to look at the data
sheet for clues to what might be causing your problems.

Thank you John. The P/N is LTC 1871. SEPIC topology similar
to the example of page 29 of the data sheet except that there is
a MOSFET driver inserted in the gate drive line. Input is 10-35V,
tolerant to 100V. Output is 12V @ 4A. L1,L2 is a dual 22uH
toroid.

TP

 

[legg]

On Sat, 22 Jan 2005 17:13:06 -0600, TP <name@usenet.com> wrote:

TP wrote:
(snip)
This problem affects about 2% of the units produced. The problem can
be corrected by replacing the controller IC, but the IC manufacturer
has tested "bad" ICs and says they meet specification. The ICs of
some date codes have about 30% failure rate while others have no
failures. The IC manufacturer has sent an applications engineer to
see the problem firsthand. We have tried all of his suggestions to no
avail. It is a Linear Technology controller IC.

On Sat, 22 Jan 2005 13:14:25 -0500, John Popelish <jpopelish@rica.net
wrote:

What Linear Technology part number? I would like to look at the data
sheet for clues to what might be causing your problems.

Thank you John. The P/N is LTC 1871. SEPIC topology similar
to the example of page 29 of the data sheet except that there is
a MOSFET driver inserted in the gate drive line. Input is 10-35V,
tolerant to 100V. Output is 12V @ 4A. L1,L2 is a dual 22uH
toroid.

As the current sensor is on the drain of the fet, delays in turning
the fet on can abort a switching cycle, due to the late high voltage
signal still being present. You have introduced a driver in series
with the chips gate drive output, adding delays in the drive waveform
that are invisible to the IC.

How the chip normally handles this delay is not evident in the
functional schematic, so you can't tell how it's being defeated by
your mod.

One way would be to detect that drive output has exceeded the typical
enhancement thresholds expected - signalling full discharge of Cdg. If
you decouple the chip drive from Cdg using an external driver, this
feedback effect would be lost.

This is pure speculation. I haven't read the data sheet closely

RL

 

[legg]

On Sun, 23 Jan 2005 01:27:04 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:

In article <qun3v0dpg9e31m3q2617r49kmo17vch5f9@4ax.com>,
legg <legg@nospam.magma.ca> wrote:
[...]
Not such a great idea in an isolated converter, as both sides of the
isolation barrier need chassis returns for locally generated common
mode currents. The chassis ties selected should shorten the return
path to the specific noise sources.

If you hook both the input and output side to the chassis, the converter
is no longer isolated. Although this may help somewhat on the EMI,
grounding both sides of the input power helps more.

The connection, in both cases, is through coupling capacitors of
suitable voltage and safety class.

It appears that this is a non-isolated application, in any event.

RL

 

[Ken Smith]

In article <qun3v0dpg9e31m3q2617r49kmo17vch5f9@4ax.com>,
legg <legg@nospam.magma.ca> wrote:
[...]

Not such a great idea in an isolated converter, as both sides of the
isolation barrier need chassis returns for locally generated common
mode currents. The chassis ties selected should shorten the return
path to the specific noise sources.

If you hook both the input and output side to the chassis, the converter
is no longer isolated. Although this may help somewhat on the EMI,
grounding both sides of the input power helps more.


--
--
kensmith@rahul.net forging knowledge

 

[legg]

On Sun, 23 Jan 2005 00:35:09 -0600, TP <name@usenet.com> wrote:

It is a 2-layer board. There is a small ground "island" under the
controller circuit with a short trace back to a central gounding
point. This island does not have high power going through it.
I found earlier that rotating the mounting position of the sense
resistor by 90Ą did appear to correct the problem at that time.
However, the problem has reoccured since.

I believe this is the first time you've mentioned the presence of a
'sensing resistor'. The referenced app circuit doesn't use one.

Please elaborate.

RL

 

[TP]

On Sat, 22 Jan 2005 18:55:15 -0500, John Popelish <jpopelish@rica.net>
wrote:

TP wrote:

John Popelish <jpopelish@rica.net> wrote:

What Linear Technology part number? I would like to look at the data
sheet for clues to what might be causing your problems.

Thank you John. The P/N is LTC 1871. SEPIC topology similar
to the example of page 29 of the data sheet except that there is
a MOSFET driver inserted in the gate drive line. Input is 10-35V,
tolerant to 100V. Output is 12V @ 4A. L1,L2 is a dual 22uH
toroid.

http://www.linear.com.cn/pdf/1871fas.pdf

Many questions come to mind, not the least of which is how you
tolerate 100 volts in, when the chip has an absolute input voltage
rating of 36, but never mind, for now.

The chip supply is taken from the output of L1 which is rectified
and goes through a linear regulator and filter. Other elements
of the circuit that are exposed to the 100V (or more) such as
input capacitor and MOSFET are rated to handle the high
voltage. This is the reason for the MOSFET driver since high
voltage MOSFETs that can operate from a 5V gate signal are
rare.

The biggest problem with designing a reliable circuit with this chip
is the unspecified gm of the error amplifier (650 umho typ., no max.
or min.) So no matter how much gain the error amplifier has, from
zero to infinity, it meets data sheet specifications. But this gain
is an integral part of the design for stability. Can you post a
layout of your board that shows how the input and output filter caps
and source of M1 relate to the common pin on the chip and the feedback
divider connections? Trace inductance and resistance and capacitor
ESR can be major players in the noise that sees its way to the error
amplifier.

I am not at liberty to post the layout. I can say that it is a
2-layer board with a ground plane area underneath the controller
IC and associated components that is not in a current path.
The IC has a bypass cap mounted extremely close to the IC.
Output caps are a combination of Oscon and ceramics.

I neglected to state that a current sense resistor is used rather
than the drain to source resistance. So the source is connected
to the SENSE pin as well as the sense resistor and both
components are physically close to the controller IC.

A longer high frequency (200 kHz), high current path is the
one from the drain to the DC coupling capacitors and inductor,
about 1 inch or so. This is unavoidable due to the confines
of the case and the physical size of those components.

In accordance with Linear Technology's recommendation,
the power components are located on one side of the IC and
the low-current components are grouped on the other side.

The error amplifier input node (pin 3) is also quite
sensitive to capacitive pickup, if not shielded by the layout. It may
be helpful to parallel the resistive divider with a capacitive divider
to lower this node's impedance (divide capacitive coupling) at high
frequencies.

I have tried adding a capacitor in parallel with the FB-to-ground
resistor.

Another big variation in the gain and stability of the current control
is the resistance of the fet switch. The lower this is, the higher
the effective gain of the current control loop. In the extreme, if
the resistance of the switch approaches zero, the gain of the current
control loop approaches the open loop gain of the current sense
comparator. Yikes. That is a big drawback of using the fet
resistance as current shunt, instead of having an actual, known
resistance in the source lead as a shunt.

I forgot to point out that I am using a current sense resistor
rather than the drain to source resistance--that didn't work
out with the particular MOSFET and current involved.

This chip gives me heartburn just looking at the data sheet. It is
optimistic enough to have been designed by a digital designer.

Although it would be nice to tweak the current circuit into
submission, I am open to chip suggestions as well.

Thanks, again.

TP