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Done it many times, but it's usually different each time....Hello,
I need a very small (2 dwords depth) show-ahead (first word fall-
through) FIFO, implemented with logic cells (registers, not RAM).
Altera megacore provides minimum depth of 4.
Does anyone have such a FIFO implemented?
The FIFO should never get into the state R1=0, R2=1.
that should be U1=0, U2=1
U1 U2 | WR RD | U1 U2 |~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
current| inputs| next | write what | write what
R1 R2 | WR RD | R1 R2 | to R1? | to R2?
try again...
On Wed, 26 Sep 2007 11:51:34 +0100,
Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:
whoops, got my register names muddled....
The FIFO should never get into the state R1=0, R2=1.
that should be U1=0, U2=1
~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
current| inputs| next | write what | write what
R1 R2 | WR RD | R1 R2 | to R1? | to R2?
try again...
U1 U2 | WR RD | U1 U2 |
apologies
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
On Wed, 26 Sep 2007 00:27:27 -0700, valdmanm@gmail.com wrote:
Hello,
I need a very small (2 dwords depth) show-ahead (first word fall-
through) FIFO, implemented with logic cells (registers, not RAM).
Altera megacore provides minimum depth of 4.
Does anyone have such a FIFO implemented?
Done it many times, but it's usually different each time....
Imagine two dword registers R1 and R2. The FIFO read port
is connected to the output of R1.
Further, imagine two single-bit flags U1 and U2 that say
whether R1 and R2 contain a valid word.
Also, we have synchronous input controls WR (write request)
and RD (take output from FIFO).
The next-state logic looks like this
(display in fixed-width font!); in the table,
* means error (attempted write to full FIFO);
- means error (attempted pop from empty FIFO)
X means error UNLESS you can provide a combinational
fall-through path from FIFO-in to FIFO-out.
The FIFO should never get into the state R1=0, R2=1.
~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
current| inputs| next | write what | write what
R1 R2 | WR RD | R1 R2 | to R1? | to R2?
~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
0 0 0 0 | 0 0 | dont-care dont-care
1 0 0 0 | 1 0 | hold dont-care
1 1 0 0 | 1 1 | hold hold
| |
0 0 1 0 | 1 0 | FIFO-in dont-care
1 0 1 0 | 1 1 | hold FIFO-in
1 1 1 0 | * * | * *
| |
0 0 1 1 | 0 0 | X X
1 0 1 1 | 1 0 | FIFO-in dont-care
1 1 1 1 | 1 1 | R2 FIFO-in
| |
0 0 0 1 | - - | - -
1 0 0 1 | 0 0 | dont-care dont-care
1 1 0 1 | 1 0 | R2 dont-care
~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
Does this make sense?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Il giorno mercoledĂŹ 26 settembre 2007 12:51:34 UTC+2, Jonathan Bromley ha scritto:
On Wed, 26 Sep 2007 00:27:27 -0700, valdmanm@gmail.com wrote:
Hello,
I need a very small (2 dwords depth) show-ahead (first word fall-
through) FIFO, implemented with logic cells (registers, not RAM).
Altera megacore provides minimum depth of 4.
Does anyone have such a FIFO implemented?
Done it many times, but it's usually different each time....
Imagine two dword registers R1 and R2. The FIFO read port
is connected to the output of R1.
Further, imagine two single-bit flags U1 and U2 that say
whether R1 and R2 contain a valid word.
Also, we have synchronous input controls WR (write request)
and RD (take output from FIFO).
The next-state logic looks like this
(display in fixed-width font!); in the table,
* means error (attempted write to full FIFO);
- means error (attempted pop from empty FIFO)
X means error UNLESS you can provide a combinational
fall-through path from FIFO-in to FIFO-out.
The FIFO should never get into the state R1=0, R2=1.
~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
current| inputs| next | write what | write what
R1 R2 | WR RD | R1 R2 | to R1? | to R2?
~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
0 0 0 0 | 0 0 | dont-care dont-care
1 0 0 0 | 1 0 | hold dont-care
1 1 0 0 | 1 1 | hold hold
| |
0 0 1 0 | 1 0 | FIFO-in dont-care
1 0 1 0 | 1 1 | hold FIFO-in
1 1 1 0 | * * | * *
| |
0 0 1 1 | 0 0 | X X
1 0 1 1 | 1 0 | FIFO-in dont-care
1 1 1 1 | 1 1 | R2 FIFO-in
| |
0 0 0 1 | - - | - -
1 0 0 1 | 0 0 | dont-care dont-care
1 1 0 1 | 1 0 | R2 dont-care
~~~|~~~|~~~|~~~|~~~|~~~|~~~~~~~~~~~~~~|~~~~~~~~~~~~~~
Does this make sense?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Old post but the code is still valid.