Slow Loadup ICFB

  • Thread starter George Ciszeski 5450
  • Start date
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George Ciszeski 5450

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Any help appreciated:

I experience a very slow loadup on a layout in a CMOS technology.

The circuits are not very large but the CPU is pegged for hours.
To avoid any possibility of network bottlenecks, all cells referenced
have been copied to a local disk.

"iostat" "vmstat" are literally quiet durning this process and CPU is 100%.

No swapping, paging or anything unusual.
But it seems "icfb" is hung or looping.

Eventually the circuit will open up but could take up to an hour
depending on the relative size.

The same thing happens when closing the circuit (if "close Data" is used.)

However, if the same circuit is opened up again without exiting Cadence,
it will open up in a few seconds as though all the info is cached.

Hardware varies but generally are SunBlades (1000, 1500, 2000, 2500)
running Solaris 2.8 and 2.9 with patch clusters.
Same circumstances whether or not circuit and cells are networked
or local.

I'm not that familiar with the technology or layout but as the sys
admin, the bosses always think I did something with the network so
they come to me.

Anyone experience anything like this?

Thanks...GeorgeC
 
George Ciszeski 5450 wrote:
The circuits are not very large but the CPU is pegged for hours.
To avoid any possibility of network bottlenecks, all cells referenced
have been copied to a local disk.

"iostat" "vmstat" are literally quiet durning this process and CPU is
100%.

No swapping, paging or anything unusual.
But it seems "icfb" is hung or looping.
Yow. Well, try doing 'truss -p' on the icfb.exe process while
it's in the "wait mode".

You'll see it stat'ing everything in your dfII hierarchy
multiple times (it seems like :) during the initial read-in,
and this is sort of slow, but not an hour.

Watch your 'netstat -i 5' output carefully. It won't show
a lot of packet count (all that stat-ing, and not much
data transfer) but watch closely for any errors. You
really should see zero in the errs columns.

You don't have old-style (cdsd) locking going, do you?

How big an icfb.exe process size do you end up with when
it's done?

Do you have *any* environments where this does *not*
happen? Compare the truss output.

The second read seeming fast like it's cached or something
seems fast because it *is* cached. That's why there's
a File->Refresh, it *never* reads something a second time
unless you tell it to.

Good luck!
 
I have seen this behavior when there are a lot of PCell instances with
most instances having unique combinations of parameters. Since the SKILL
code behind the PCell must evaluate for each parameter combination, you
can spend a lot of time creating the sub-masters. When you "Close Data",
they all go away and the memory gets returned to the free list which is
an expensive proposition for large numbers of small memory blocks.

I would use /usr/proc/bin/pstack to see if you have a function like
pcellEval, evalParamCell, or something similar on the call stack. The
presence of such a function on a regular basis would indicate you are
evaluating a great number of PCells. Or that the PCells are very complex
or very poorly written.

On Thu, 16 Dec 2004 14:28:35 -0500, George Ciszeski 5450
<cad@anadigics.com> wrote:

Any help appreciated:

I experience a very slow loadup on a layout in a CMOS technology.

The circuits are not very large but the CPU is pegged for hours.
To avoid any possibility of network bottlenecks, all cells referenced
have been copied to a local disk.

"iostat" "vmstat" are literally quiet durning this process and CPU is 100%.

No swapping, paging or anything unusual.
But it seems "icfb" is hung or looping.

Eventually the circuit will open up but could take up to an hour
depending on the relative size.

The same thing happens when closing the circuit (if "close Data" is used.)

However, if the same circuit is opened up again without exiting Cadence,
it will open up in a few seconds as though all the info is cached.

Hardware varies but generally are SunBlades (1000, 1500, 2000, 2500)
running Solaris 2.8 and 2.9 with patch clusters.
Same circumstances whether or not circuit and cells are networked
or local.

I'm not that familiar with the technology or layout but as the sys
admin, the bosses always think I did something with the network so
they come to me.

Anyone experience anything like this?

Thanks...GeorgeC
 
Bingo!


Right after I sent out this call for help, we started looking the pcells.
We have "rod capacitors" which have turned out to be the culprit.

We're (our tools department) are looking into a workaround as we speak
as well as pushing forward to releasing IC5.X which I understand handle this
better.

Many thanks...George


"Diva Physical Verification" <diva@cadence.com> wrote in message
news:6nl4s0hl22tgm4ckck0jcpmiac9k308a5u@4ax.com...
I have seen this behavior when there are a lot of PCell instances with
most instances having unique combinations of parameters. Since the SKILL
code behind the PCell must evaluate for each parameter combination, you
can spend a lot of time creating the sub-masters. When you "Close Data",
they all go away and the memory gets returned to the free list which is
an expensive proposition for large numbers of small memory blocks.

I would use /usr/proc/bin/pstack to see if you have a function like
pcellEval, evalParamCell, or something similar on the call stack. The
presence of such a function on a regular basis would indicate you are
evaluating a great number of PCells. Or that the PCells are very complex
or very poorly written.

On Thu, 16 Dec 2004 14:28:35 -0500, George Ciszeski 5450
cad@anadigics.com> wrote:

Any help appreciated:

I experience a very slow loadup on a layout in a CMOS technology.

The circuits are not very large but the CPU is pegged for hours.
To avoid any possibility of network bottlenecks, all cells referenced
have been copied to a local disk.

"iostat" "vmstat" are literally quiet durning this process and CPU is
100%.

No swapping, paging or anything unusual.
But it seems "icfb" is hung or looping.

Eventually the circuit will open up but could take up to an hour
depending on the relative size.

The same thing happens when closing the circuit (if "close Data" is
used.)

However, if the same circuit is opened up again without exiting Cadence,
it will open up in a few seconds as though all the info is cached.

Hardware varies but generally are SunBlades (1000, 1500, 2000, 2500)
running Solaris 2.8 and 2.9 with patch clusters.
Same circumstances whether or not circuit and cells are networked
or local.

I'm not that familiar with the technology or layout but as the sys
admin, the bosses always think I did something with the network so
they come to me.

Anyone experience anything like this?

Thanks...GeorgeC
 

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