Slightly OT: Digital watch circuits

[Tim Wescott]

Someone on reddit asked about quartz watches, and I told them that one
way to do it would be a counter chain, with the counter outputs feeding
decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly reduce
the total transistor count by having a 7-segment clock, with seven or
fewer flip-flops and various bits of logic to generate the next state and
the current readout.

I assume that digital watch IC's are some totally custom thing, and I
wouldn't be surprised if there aren't a bunch of factories out there that
have lost the recipe and just have the masks. But -- does anyone know
what's done?

Thanks.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

 

[Kevin Neilson]

On Friday, December 30, 2016 at 2:03:38 PM UTC-7, Tim Wescott wrote:

Someone on reddit asked about quartz watches, and I told them that one
way to do it would be a counter chain, with the counter outputs feeding
decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly reduce
the total transistor count by having a 7-segment clock, with seven or
fewer flip-flops and various bits of logic to generate the next state and
the current readout.

I seem to remember that the original watch crystals were 32.768kHz, so I assumed that was so they could use a simple 15-FF ripple counter for a divider so as to get the lowest gate count and power. I assume the rest was, like you said, 3 or 4 counters (mod-10, mod-6, and mod-12) and some 7-seg decoders. I can't remember how you set the time on those. It could have been as simple as having a button that would bypass a few stages of the ripple counter so you could speed up the clock until you got to the right time.

 

[rickman]

On 12/30/2016 4:03 PM, Tim Wescott wrote:

Someone on reddit asked about quartz watches, and I told them that one
way to do it would be a counter chain, with the counter outputs feeding
decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly reduce
the total transistor count by having a 7-segment clock, with seven or
fewer flip-flops and various bits of logic to generate the next state and
the current readout.

I assume that digital watch IC's are some totally custom thing, and I
wouldn't be surprised if there aren't a bunch of factories out there that
have lost the recipe and just have the masks. But -- does anyone know
what's done?

I'm not sure what you are confused about. I also don't understand your
idea of somehow using just 7 FFs to manage a clock display.

The original digital clocks did use a counter chain which generated
either a 1 pps signal to drive the time counters if keeping seconds or a
1 pp minute signal to drive the time counter if not keeping seconds.

Today there is little reason to minimize transistor counts. Transistors
are nearly free even if you make a million dies. They use a 4 bit CPU
to do all the work which likely includes dividing the 32.768 kHz clock
to 1 second.

You can check the Epson web site for CPU chips which I believe are the
type of 4 bit CPUs they use in watches.

Remember that watches often do a lot more than just tell time these days.

--

Rick C

 

[Jean-marc Lienher]

rickman wrote:

You can check the Epson web site for CPU chips which I believe are the
type of 4 bit CPUs they use in watches.

Epson or if you want the Swiss touch you can check the Swatch group web
site:
http://www.emmicroelectronic.com/products/microcontrollers/lcd-driver/em6627

 

[rickman]

On 12/31/2016 8:42 AM, Jean-marc Lienher wrote:

rickman wrote:
You can check the Epson web site for CPU chips which I believe are the
type of 4 bit CPUs they use in watches.

Epson or if you want the Swiss touch you can check the Swatch group web
site:
http://www.emmicroelectronic.com/products/microcontrollers/lcd-driver/em6627

Thank you. I have seen these as well, but couldn't remember the
company. I think I have seen plans for a radio controlled clock using a
demodulator chip and an EMmicro CPU. Great power consumption.

--

Rick C

 

[Tim Wescott]

On Sat, 31 Dec 2016 02:54:41 -0500, rickman wrote:

On 12/30/2016 4:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that one
way to do it would be a counter chain, with the counter outputs feeding
decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly reduce
the total transistor count by having a 7-segment clock, with seven or
fewer flip-flops and various bits of logic to generate the next state
and the current readout.

I assume that digital watch IC's are some totally custom thing, and I
wouldn't be surprised if there aren't a bunch of factories out there
that have lost the recipe and just have the masks. But -- does anyone
know what's done?

I'm not sure what you are confused about. I also don't understand your
idea of somehow using just 7 FFs to manage a clock display.

The original digital clocks did use a counter chain which generated
either a 1 pps signal to drive the time counters if keeping seconds or a
1 pp minute signal to drive the time counter if not keeping seconds.

Today there is little reason to minimize transistor counts. Transistors
are nearly free even if you make a million dies. They use a 4 bit CPU
to do all the work which likely includes dividing the 32.768 kHz clock
to 1 second.

You can check the Epson web site for CPU chips which I believe are the
type of 4 bit CPUs they use in watches.

Remember that watches often do a lot more than just tell time these
days.

Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

--
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work! See my website if you're interested
http://www.wescottdesign.com

 

[rickman]

On 12/31/2016 1:32 PM, Tim Wescott wrote:

On Sat, 31 Dec 2016 02:54:41 -0500, rickman wrote:

On 12/30/2016 4:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that one
way to do it would be a counter chain, with the counter outputs feeding
decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly reduce
the total transistor count by having a 7-segment clock, with seven or
fewer flip-flops and various bits of logic to generate the next state
and the current readout.

I assume that digital watch IC's are some totally custom thing, and I
wouldn't be surprised if there aren't a bunch of factories out there
that have lost the recipe and just have the masks. But -- does anyone
know what's done?

I'm not sure what you are confused about. I also don't understand your
idea of somehow using just 7 FFs to manage a clock display.

The original digital clocks did use a counter chain which generated
either a 1 pps signal to drive the time counters if keeping seconds or a
1 pp minute signal to drive the time counter if not keeping seconds.

Today there is little reason to minimize transistor counts. Transistors
are nearly free even if you make a million dies. They use a 4 bit CPU
to do all the work which likely includes dividing the 32.768 kHz clock
to 1 second.

You can check the Epson web site for CPU chips which I believe are the
type of 4 bit CPUs they use in watches.

Remember that watches often do a lot more than just tell time these
days.

Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

I don't think 7 FFs per digit was ever used... but then I never reverse
engineered a watch. I believe every clock chip data sheet I've ever
seen showed a direct binary counter to generate the 1 pps or 1 ppm
clock. Then the time was kept by a chain of 4 bit decimal counters some
of which only go up to 6 or 2 depending on the position. The digits
were then driven by BCD to 7 segment decoders. But I can't say for sure
that is how they designed custom watch chips. I think you would have to
ask the designer to be certain.

I don't know for sure how long 4 bit MCUs have been used for watches,
but you can look back to see when they started making watches with the
date and other more complex functions. A 4 bit MCU is not very complex
and it wouldn't require much in the way of functionality to make a CPU
the right choice over discrete logic. Leap year at century and
millennial boundaries would be a bit much for discrete counters.

It seems to be hard to find any info with Google. There are so many
Linux based watches these days that none of the old stuff shows up.

--

Rick C

 

[Tim Wescott]

On Sat, 31 Dec 2016 14:08:01 -0500, rickman wrote:

On 12/31/2016 1:32 PM, Tim Wescott wrote:
On Sat, 31 Dec 2016 02:54:41 -0500, rickman wrote:

On 12/30/2016 4:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that
one way to do it would be a counter chain, with the counter outputs
feeding decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly
reduce the total transistor count by having a 7-segment clock, with
seven or fewer flip-flops and various bits of logic to generate the
next state and the current readout.

I assume that digital watch IC's are some totally custom thing, and I
wouldn't be surprised if there aren't a bunch of factories out there
that have lost the recipe and just have the masks. But -- does
anyone know what's done?

I'm not sure what you are confused about. I also don't understand
your idea of somehow using just 7 FFs to manage a clock display.

The original digital clocks did use a counter chain which generated
either a 1 pps signal to drive the time counters if keeping seconds or
a 1 pp minute signal to drive the time counter if not keeping seconds.

Today there is little reason to minimize transistor counts.
Transistors are nearly free even if you make a million dies. They use
a 4 bit CPU to do all the work which likely includes dividing the
32.768 kHz clock to 1 second.

You can check the Epson web site for CPU chips which I believe are the
type of 4 bit CPUs they use in watches.

Remember that watches often do a lot more than just tell time these
days.

Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

I don't think 7 FFs per digit was ever used... but then I never reverse
engineered a watch. I believe every clock chip data sheet I've ever
seen showed a direct binary counter to generate the 1 pps or 1 ppm
clock. Then the time was kept by a chain of 4 bit decimal counters some
of which only go up to 6 or 2 depending on the position. The digits
were then driven by BCD to 7 segment decoders. But I can't say for sure
that is how they designed custom watch chips. I think you would have to
ask the designer to be certain.

I don't know for sure how long 4 bit MCUs have been used for watches,
but you can look back to see when they started making watches with the
date and other more complex functions. A 4 bit MCU is not very complex
and it wouldn't require much in the way of functionality to make a CPU
the right choice over discrete logic. Leap year at century and
millennial boundaries would be a bit much for discrete counters.

It seems to be hard to find any info with Google. There are so many
Linux based watches these days that none of the old stuff shows up.

Linux watches. Jeeze. When I was a kid, watches had springs and wheels
and little things that went "ziiiiing!" when you tried to take them apart
(I think they were called escapements, maybe because of their habits).

--
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work! See my website if you're interested
http://www.wescottdesign.com

 

[rickman]

On 1/1/2017 12:49 AM, Tim Wescott wrote:

On Sat, 31 Dec 2016 14:08:01 -0500, rickman wrote:

On 12/31/2016 1:32 PM, Tim Wescott wrote:
On Sat, 31 Dec 2016 02:54:41 -0500, rickman wrote:

On 12/30/2016 4:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that
one way to do it would be a counter chain, with the counter outputs
feeding decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly
reduce the total transistor count by having a 7-segment clock, with
seven or fewer flip-flops and various bits of logic to generate the
next state and the current readout.

I assume that digital watch IC's are some totally custom thing, and I
wouldn't be surprised if there aren't a bunch of factories out there
that have lost the recipe and just have the masks. But -- does
anyone know what's done?

I'm not sure what you are confused about. I also don't understand
your idea of somehow using just 7 FFs to manage a clock display.

The original digital clocks did use a counter chain which generated
either a 1 pps signal to drive the time counters if keeping seconds or
a 1 pp minute signal to drive the time counter if not keeping seconds.

Today there is little reason to minimize transistor counts.
Transistors are nearly free even if you make a million dies. They use
a 4 bit CPU to do all the work which likely includes dividing the
32.768 kHz clock to 1 second.

You can check the Epson web site for CPU chips which I believe are the
type of 4 bit CPUs they use in watches.

Remember that watches often do a lot more than just tell time these
days.

Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

I don't think 7 FFs per digit was ever used... but then I never reverse
engineered a watch. I believe every clock chip data sheet I've ever
seen showed a direct binary counter to generate the 1 pps or 1 ppm
clock. Then the time was kept by a chain of 4 bit decimal counters some
of which only go up to 6 or 2 depending on the position. The digits
were then driven by BCD to 7 segment decoders. But I can't say for sure
that is how they designed custom watch chips. I think you would have to
ask the designer to be certain.

I don't know for sure how long 4 bit MCUs have been used for watches,
but you can look back to see when they started making watches with the
date and other more complex functions. A 4 bit MCU is not very complex
and it wouldn't require much in the way of functionality to make a CPU
the right choice over discrete logic. Leap year at century and
millennial boundaries would be a bit much for discrete counters.

It seems to be hard to find any info with Google. There are so many
Linux based watches these days that none of the old stuff shows up.

Linux watches. Jeeze. When I was a kid, watches had springs and wheels
and little things that went "ziiiiing!" when you tried to take them apart
(I think they were called escapements, maybe because of their habits).

Yeah, I'm sure phones where those things you could club a person to
death with too rather than a popular way of watching your favorite TV
show. Back then the picture phone was something you saw at a World's Fair.

--

Rick C

 

[Theo Markettos]

Tim Wescott <tim@seemywebsite.com> wrote:

Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

The advert for one of the first (Sinclair Black Watch, 1975) describes the
chip:

<quote>
The chip...
The heart of the Black Watch is a unique IC designed by Sinclair and Custom
-built for them using state -of- the -art technology - integrated injection
logic. This chip of silicon measures only 3 mm x 3 mm and contains over
2000 transistors.The circuit includes
a) reference oscillator
b) divider chain
c) decoder circuits
d) display inhibit circuits
e) display driving circuits.
The chip is totally designed and manufactured in the UK, and is
the first design to incorporate all circuitry for a digital watch on a
single chip.

....and how it works
A crystal -controlled reference is used to
drive a chain of 15 binary dividers which reduce the frequency from 32,768
Hz to 1 Hz.This accurate signal is then counted into units of seconds,
minutes, and hours, and on request the stored information is processed by
the decoders and display drivers to feed the four 7- segment LED displays.
When the display is not in operation, special power- saving circuits on the
chip reduce current consumption to only a few microamps.
</quote>

http://www.americanradiohistory.com/Archive-Practical/Wireless/70s/PW-1976-03.pdf
page 68
(fab was supposed to be Mullard but they pulled out, I think it was
eventually ITT)

Theo

 

[Anssi Saari]

rickman <gnuarm@gmail.com> writes:

I don't know for sure how long 4 bit MCUs have been used for watches,
but you can look back to see when they started making watches with the
date and other more complex functions. A 4 bit MCU is not very
complex and it wouldn't require much in the way of functionality to
make a CPU the right choice over discrete logic. Leap year at century
and millennial boundaries would be a bit much for discrete counters.

I vaguely remember getting a digital wristwatch in the late 70s,
Japanese Citizen I think. I'm pretty sure it had two times (i.e. other
timezone for travel and such, no idea if it was just whole hour
offsets), calendar, stopwatch with 1/100th second accuracy. Nothing more
than that, no alarm or timer that were pretty common early
on. Unfortunately I can't remember if the calendar could handle leap
years or not. BTW, that seems to be a common thing to skip with today's
analog wristwatches too, at least with the cheaper ones.

 

[BobH]

On 12/30/2016 02:03 PM, Tim Wescott wrote:

Someone on reddit asked about quartz watches, and I told them that one
way to do it would be a counter chain, with the counter outputs feeding
decimal-to-7-segment decoders.

But, what is actually done? I could see how one might possibly reduce
the total transistor count by having a 7-segment clock, with seven or
fewer flip-flops and various bits of logic to generate the next state and
the current readout.

I assume that digital watch IC's are some totally custom thing, and I
wouldn't be surprised if there aren't a bunch of factories out there that
have lost the recipe and just have the masks. But -- does anyone know
what's done?

Thanks.

Looking at a copy of the National Semiconductor 1977 MOS LSI data book,
they have several watch IC's shown. From the block diagrams, it looks
like they are using dividers off the crystal oscillator down to 4KHz and
1Hz, followed by "Display and Set Control Logic". There are individual
signals down to the hours, minutes and seconds counters. The counter
outputs go down to "Select Counter Logic" which feeds a "7 segment
decoder" block.
The block diagrams for the MM5829, MM5860/MM58601, and MM5885 chips are
all fairly similar, in that they show separate counters for hours,
minutes and seconds.
The MM5890 "LCD Chronograph" chip has a stop watch built in and it shows
separate counters for the stop watch timing, feeding into the counter
select logic block.

It would be possible to implement a state machine that counts in 7
segment format, but it would be ugly to do, and probably larger than
simple ripple counters feeding into a shared bcd to 7 segment decoder.

Happy New Year,
BobH

 

[Tim Wescott]

On Mon, 02 Jan 2017 14:35:36 +0000, Theo Markettos wrote:

Tim Wescott <tim@seemywebsite.com> wrote:
Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

The advert for one of the first (Sinclair Black Watch, 1975) describes
the chip:

quote
The chip...
The heart of the Black Watch is a unique IC designed by Sinclair and
Custom -built for them using state -of- the -art technology - integrated
injection logic. This chip of silicon measures only 3 mm x 3 mm and
contains over 2000 transistors.The circuit includes a) reference
oscillator b) divider chain c) decoder circuits d) display inhibit
circuits e) display driving circuits.
The chip is totally designed and manufactured in the UK, and is the
first design to incorporate all circuitry for a digital watch on a
single chip.

...and how it works A crystal -controlled reference is used to drive a
chain of 15 binary dividers which reduce the frequency from 32,768 Hz to
1 Hz.This accurate signal is then counted into units of seconds,
minutes, and hours, and on request the stored information is processed
by the decoders and display drivers to feed the four 7- segment LED
displays.
When the display is not in operation, special power- saving circuits on
the chip reduce current consumption to only a few microamps.
/quote

http://www.americanradiohistory.com/Archive-Practical/Wireless/70s/
PW-1976-03.pdf
page 68 (fab was supposed to be Mullard but they pulled out, I think it
was eventually ITT)

Theo

Wow. I think that 2000 transistors is less than half the way to a 4-bit
micro, isn't it? So maybe they went that way early on.

--
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work! See my website if you're interested
http://www.wescottdesign.com

 

[Tim Wescott]

On Mon, 02 Jan 2017 08:07:39 -0700, BobH wrote:

On 12/30/2016 02:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that one

<snip>

It would be possible to implement a state machine that counts in 7
segment format, but it would be ugly to do, and probably larger than
simple ripple counters feeding into a shared bcd to 7 segment decoder.

That answers that question, except for the residual "probably".

--
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work! See my website if you're interested
http://www.wescottdesign.com

 

[BobH]

On 01/02/2017 11:02 AM, Tim Wescott wrote:

On Mon, 02 Jan 2017 08:07:39 -0700, BobH wrote:

On 12/30/2016 02:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that one

snip

It would be possible to implement a state machine that counts in 7
segment format, but it would be ugly to do, and probably larger than
simple ripple counters feeding into a shared bcd to 7 segment decoder.

That answers that question, except for the residual "probably".

Sprechen Sie Verilog? Give it a try.

I have done a lot of state machine design through the years and I can't
imagine why a 7 segment counting state machine would not be larger than
a simple ripple binary counter. I put the "probably" in because this is
usenet, and the probability of getting in a flame war over something
like this seems pretty high.

If you think about it, the muxed display implementation, with 3 bcd
ripple counters sharing one bcd to 7 segment decoder should be way
smaller than 4 7 bit counters with complex next state logic.

BobH

 

[rickman]

On 1/2/2017 9:35 AM, Theo Markettos wrote:

Tim Wescott <tim@seemywebsite.com> wrote:
Seven FF _per digit_. I'm more interested in what was done back in the
day. Do you know how long the 4-bit CPU has been used?

The advert for one of the first (Sinclair Black Watch, 1975) describes the
chip:

quote
The chip...
The heart of the Black Watch is a unique IC designed by Sinclair and Custom
-built for them using state -of- the -art technology - integrated injection
logic. This chip of silicon measures only 3 mm x 3 mm and contains over
2000 transistors.The circuit includes
a) reference oscillator
b) divider chain
c) decoder circuits
d) display inhibit circuits
e) display driving circuits.
The chip is totally designed and manufactured in the UK, and is
the first design to incorporate all circuitry for a digital watch on a
single chip.

...and how it works
A crystal -controlled reference is used to
drive a chain of 15 binary dividers which reduce the frequency from 32,768
Hz to 1 Hz.This accurate signal is then counted into units of seconds,
minutes, and hours, and on request the stored information is processed by
the decoders and display drivers to feed the four 7- segment LED displays.
When the display is not in operation, special power- saving circuits on the
chip reduce current consumption to only a few microamps.
/quote

http://www.americanradiohistory.com/Archive-Practical/Wireless/70s/PW-1976-03.pdf
page 68
(fab was supposed to be Mullard but they pulled out, I think it was
eventually ITT)

Good find!

--

Rick C

 

[Tim Wescott]

On Mon, 02 Jan 2017 14:57:03 -0700, BobH wrote:

On 01/02/2017 11:02 AM, Tim Wescott wrote:
On Mon, 02 Jan 2017 08:07:39 -0700, BobH wrote:

On 12/30/2016 02:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that
one

snip

It would be possible to implement a state machine that counts in 7
segment format, but it would be ugly to do, and probably larger than
simple ripple counters feeding into a shared bcd to 7 segment decoder.

That answers that question, except for the residual "probably".

Sprechen Sie Verilog? Give it a try.

I have done a lot of state machine design through the years and I can't
imagine why a 7 segment counting state machine would not be larger than
a simple ripple binary counter. I put the "probably" in because this is
usenet, and the probability of getting in a flame war over something
like this seems pretty high.

If you think about it, the muxed display implementation, with 3 bcd
ripple counters sharing one bcd to 7 segment decoder should be way
smaller than 4 7 bit counters with complex next state logic.

I'm really more a systems egghead with solid software (and, oddly, analog
circuit) design skills. I don't do much FPGA work, and what I end up
doing is nothing to write home about -- I generally know what's possible
in pure digital-land, and can work with the real logic guys to make it
happen.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

 

[rickman]

On 1/2/2017 6:04 PM, Tim Wescott wrote:

On Mon, 02 Jan 2017 14:57:03 -0700, BobH wrote:

On 01/02/2017 11:02 AM, Tim Wescott wrote:
On Mon, 02 Jan 2017 08:07:39 -0700, BobH wrote:

On 12/30/2016 02:03 PM, Tim Wescott wrote:
Someone on reddit asked about quartz watches, and I told them that
one

snip

It would be possible to implement a state machine that counts in 7
segment format, but it would be ugly to do, and probably larger than
simple ripple counters feeding into a shared bcd to 7 segment decoder.

That answers that question, except for the residual "probably".

Sprechen Sie Verilog? Give it a try.

I have done a lot of state machine design through the years and I can't
imagine why a 7 segment counting state machine would not be larger than
a simple ripple binary counter. I put the "probably" in because this is
usenet, and the probability of getting in a flame war over something
like this seems pretty high.

If you think about it, the muxed display implementation, with 3 bcd
ripple counters sharing one bcd to 7 segment decoder should be way
smaller than 4 7 bit counters with complex next state logic.

I'm really more a systems egghead with solid software (and, oddly, analog
circuit) design skills. I don't do much FPGA work, and what I end up
doing is nothing to write home about -- I generally know what's possible
in pure digital-land, and can work with the real logic guys to make it
happen.

I don't know directly wiring 7 FFs for each digit is a horrible idea.
That would be coded as a FSM by connecting present states with next
states...

SUBTYPE DigitType is unsigned(6 downto 0);

CONSTANT DigitZero : DigitType := "0111111"
CONSTANT DigitOne : DigitType := "0000110"
CONSTANT DigitTwo : DigitType := "1011011"
CONSTANT DigitThree : DigitType := "1001111"
CONSTANT DigitFour : DigitType := "1100110"
CONSTANT DigitFive : DigitType := "1101101"
CONSTANT DigitSix : DigitType := "1111101"
CONSTANT DigitSeven : DigitType := "0000111"
CONSTANT DigitEight : DigitType := "1111111"
CONSTANT DigitNine : DigitType := "1100111"

SIGNAL DigitCur : DigitType;
SIGNAL CntEnable : std_logic;

PROCESS (clk, rst) BEGIN
IF (rst) THEN
DigitCur <= DigitZero ;
ELSIF rising_edge(clk) THEN
IF (CntEnable) THEN
case DigitCur is
when DigitZero => DigitCur <= DigitOne;
when DigitOne => DigitCur <= DigitTwo;
when DigitTwo => DigitCur <= DigitThree;
when DigitThree => DigitCur <= DigitFour;
when DigitFour => DigitCur <= DigitFive;
when DigitFive => DigitCur <= DigitSix;
when DigitSix => DigitCur <= DigitSeven;
when DigitSeven => DigitCur <= DigitEight;
when DigitEight => DigitCur <= DigitNine;
when DigitNine => DigitCur <= DigitZero;
when others => DigitCur <= DigitZero;
end case;
END IF;
END IF;
END PROCESS;

I recall coding a 7 seg to decimal decoder in software once and you
don't even need all the bits as input to determine the next state. I
think I used five. The above code ends up being 7 independent FSM, one
for each bit dependent on what ever ends up being minimal. So I don't
think the logic is very complex. The only real complexity is using 7
FFs instead of 4. A FF has some dozen or more gates and I expect the
PS->NS random logic is less that that for each bit.

For example, the bit for the 'a' segment, the one at the top of the
digit, is only a zero for the 1 and the 4. The preceding states are 0
and 3. To decode those two you can xor segments f and g, then and with
segment c and invert. a_next := not (c and (f_cur xor g_cur)) That's
pretty simple function, one 4 input LUT.

So maybe directly coding the digits with a 7 bit FSM is not such a bad
idea.

--

Rick C

 

[Kevin Neilson]

Wow. I think that 2000 transistors is less than half the way to a 4-bit
micro, isn't it? So maybe they went that way early on.

I'm sure they must've used a custom circuit initially. The text about the "display inhibit" circuit reminded me that the original digital watches were luminous (not LCD) and you had to push a button to display the time, in order to save the battery.

It would be an interesting homework problem to design a digital watch chip with the fewest 2-input gates. Gated clocks, glitches, and latches all allowed.

 

[GaborSzakacs]

Kevin Neilson wrote:

Wow. I think that 2000 transistors is less than half the way to a 4-bit
micro, isn't it? So maybe they went that way early on.

I'm sure they must've used a custom circuit initially. The text about the "display inhibit" circuit reminded me that the original digital watches were luminous (not LCD) and you had to push a button to display the time, in order to save the battery.

It would be an interesting homework problem to design a digital watch chip with the fewest 2-input gates. Gated clocks, glitches, and latches all allowed.

Check out this article comparing the first Pulsar digital watch
to the new Apple watch:

https://dealspotr.com/article/apple-watch-has-come-a-long-way-since-the-first-digital-watch

It seems that this model (produced only in small quantity) did not have
a custom chip (article quotes 25 chips in the watch). It had a button
to illuminate the display and two magnet-activated switches to set the
time (hours and minutes). Modern digital alarm clocks still use the
same clunky Hour and Minute buttons to set time, which is very
frustrating when you want to move the time back by one minute or one
hour.

A friend of mine worked at Fairchild not long after the first digital
watches came out. He told me that they made chips for digital clocks
that included a 4-bit micro. Chips for AC plug-in clocks used 60 Hz
from the power mains for the time base, with a self-calibrated (against
the power mains frequency) internal oscillator for battery-backup mode.


--
Gabor