Slice Usage

[Turj]

Dear all,

I am using XST 12.1 for sythensis and for the first time I had a look at
how many slices are occupied by my design. I have to say, I am bit
overwhelmed by the results, with Virtex II you essentially got one
figure which was the total of the slices.

In Virtex 5, XST seems break this down as follows:

Design Summary:
Slice Logic Utilization:
Number of Slice Registers: 3,127 out of 28,800 9%
Number used as Flip Flops: 3,127
Number of Slice LUTs: 7,521 out of 28,800 25%
Number used as logic: 7,256 out of 28,800 25%
Number using O6 output only: 7,001
Number using O5 output only: 68
Number using O5 and O6: 75
Number used as Memory: 37 out of 7,680 1%
Number used as Shift Register: 37
Number using O6 output only: 37
Number used as exclusive route-thru: 3
Number of route-thrus: 72
Number using O6 output only: 60
Number using O5 output only: 9

Slice Logic Distribution:
Number of occupied Slices: 2,451 out of 7,200 32%
Number of LUT Flip Flop pairs used: 8,625
Number with an unused Flip Flop: 5,001 out of 7,707 63%
Number with an unused LUT: 507 out of 7,707 5%
Number of fully used LUT-FF pairs: 2,532 out of 7,707 31%
Number of unique control sets: 233

So what it now the number of total slices occupied on my board? Which
ones do I have to add up?

Maybe: Number of occupied slices + Number of Slice Registers + Number
Used as Logic?

thanks,
Turj

 

[Chris Maryan]

"Number of occupied slices" is the total number of slices used. "Number of slice registers" is the number of FFs used in the whole FPGA, there are 4 FFs and 4 LUTs to a slice in a V5 (7200*4 = 28800).

"Number used as logic" is the number of LUTs used as a true LUT. A LUT can also be used as distributed RAM (Number used as Memory) (see Xilinx docs) or as a shift register (See SRL in the docs).

A slice can have anywhere from 0 to all 4 of it's FFs used, same goes for the LUTs. Sometimes a slice is partially empty because the placer chooses to group the LUTs/FFs that way for no good reason, sometimes there are legitimate reasons why certain groups of FFs can't be put in the same slice as some others (look for "control sets" in the Xilinx documentation).

If you are trying to get an idea of how big your design is, the number of LUTs (Number of Slice LUTs) or the number of FFs (Number of Slice Registers) is usually a good start - In my experience, MAP/PAR are able to fill up to about 75-80% of the FFs or LUTs in a chip before it becomes difficult to fit everything.

Chris

 

[Thomas Womack]

In article <ikjqfr$uah$1@speranza.aioe.org>, Turj <Turj@hotmail.com> wrote:

Dear all,

I am using XST 12.1 for sythensis and for the first time I had a look at
how many slices are occupied by my design. I have to say, I am bit
overwhelmed by the results, with Virtex II you essentially got one
figure which was the total of the slices.

In Virtex 5, XST seems break this down as follows:

Design Summary:
Number of Slice Registers: 3,127 out of 28,800 9%
Number of Slice LUTs: 7,521 out of 28,800 25%

Slice Logic Distribution:
Number of occupied Slices: 2,451 out of 7,200 32%

So what it now the number of total slices occupied on my board? Which
ones do I have to add up?

'Number of occupied slices' is the number you want; the slices are
quite big (each contains four registers and four LUTs, with not all of
them necessarily being used). At the moment, you could double the
size of your design with no trouble; you might be able to triple it
assuming things pack nicely (you'd be using 75% of the LUTs and maybe
the software would be able to pack them into less than the 96% of the
slices which simply writing the current design down three times would
occupy); it would be unwise to attempt to quadruple it.

Tom