slice bound doesn't belong to range....

[Hilko]

Hi

i'm a beginner in vhdl. i have some experiences in AHDL. In AHDL the
following code is no problem:

reg_a[7..0] = reg_b[15..8];
where reg_a and reg_b are vectors of dff's.

The same in VHDL

signal_a(7 downto 0) = signal_b(15 downto 8); doesn't work. The
following error occurs:

VHDL error...: left bound (15) of slice must belong to range (7 downto
0) of corresponding object

What is the correct way to do so in VHDL ???

Thanks
Hilko

 

[Mike Treseler]

Hilko wrote:

i'm a beginner in vhdl. i have some experiences in AHDL. In AHDL the
following code is no problem:
reg_a[7..0] = reg_b[15..8];
where reg_a and reg_b are vectors of dff's.

What is the correct way to do so in VHDL ???

Consider this entity:

entity sync_template is
generic (vec_len : positive := 8);
port (
clock : in std_ulogic;
reset : in std_ulogic;
a : in std_ulogic;
q : out std_logic_vector(vec_len-1 downto 0)
);
end entity sync_template;

There is often more than one assignment of
the same type in a vhdl design. One way
to handle this cleanly is by declaring
a subtype, say vec_t:

subtype vec_t is unsigned(vec_len-1 downto 0);
constant vec_init : vec_t := "10110011";
variable reg_v : vec_t ;

Once I have declared the above, I can initialize reg_v like this:
reg_v := vec_init;

and I can update it like this:

if a='1' then
reg_v := rotate_left(reg_v,1);
end if;

and I can output its value to a port like this:

q <= std_logic_vector(reg_v);

See the full architecture here:
http://home.comcast.net/~mike_treseler/sync_template.vhd

-- Mike Treseler