S
Shenli
Guest
Hi all,
When reading Janick's "Writing Testbench Using SystemVerilog", I found
"Slave Generators" section from P253 to P255 is confusing.
In Sample 5-71,
Code:
forever begin
...
pmem.fetch(addr,opcode); // opcode is input, and addr is output
opcode = generate_opcode(addr);
...
end
It seems we fetch addr from opcode, then we generate opcode from addr.
1. Why not generate_opcode(addr) directly? Thanks!
Best regards,
Davy
When reading Janick's "Writing Testbench Using SystemVerilog", I found
"Slave Generators" section from P253 to P255 is confusing.
In Sample 5-71,
Code:
forever begin
...
pmem.fetch(addr,opcode); // opcode is input, and addr is output
opcode = generate_opcode(addr);
...
end
It seems we fetch addr from opcode, then we generate opcode from addr.
1. Why not generate_opcode(addr) directly? Thanks!
Best regards,
Davy