Slack gets worst as I relax timing

[tushit]

Hi,
I am using QuartusII 3.0. I setup a tsu requirement on some input pins
and quartus did a P&R and said it could not meet the tsu by 0.5ns on
only one of the paths. So I relaxed my tsu by about 1ns on all pins
and did an incremental fitting. Now Quartus came back and said it
could not meet timing on about 15 paths by 1.5ns. Why is this? Is
there anyway of adding more predictibility in the P&R of Quartus?
Thanks & regards
tushit

 

[Vaughn Betz]

I am using QuartusII 3.0. I setup a tsu requirement on some input pins
and quartus did a P&R and said it could not meet the tsu by 0.5ns on
only one of the paths. So I relaxed my tsu by about 1ns on all pins
and did an incremental fitting. Now Quartus came back and said it
could not meet timing on about 15 paths by 1.5ns. Why is this? Is
there anyway of adding more predictibility in the P&R of Quartus?
Thanks & regards
tushit

Hi Tushit,

If you simply want to change your timing requirements and re-do timing
analysis, you don't have to re-run the fitter. Just run the timing
analyzer (quartus_tan).

Most people use incremental fitting when they have a small change to
the circuit, rather than a timing requirement change. In that case,
incremental fitting usually results in a small timing change (there is
generally some small change in timing with incremental fitting, since
the routing changes --incremental fitting only tries to re-use the
placement).

Did you notice if the logic cell count was different in the two
compiles? There are some algorithms before fitting that would be
affected by this timing requirement change, and this could change the
netlist enough that incremental fitting wouldn't be able to maintain a
placement similar to what you had in the first fit.

For "hard" control over fitting results, you can back-annotate your
placement. This will lock every LE etc. in your design down, which is
OK if you don't plan on changing your design source anymore, but
definitely isn't a good idea if you're still going to be changing
source and resynthesizing. If you back-annotate both placement and
routing, you lock everything down, for even more control.

I'd be interested in getting this circuit as a test case so we can see
why incremental fitting produced a noticable timing change. We'd only
use it to debug this issue and as a CAD tool test case. If you're
interested, send me the Quartus archive at vbetz@altera.com.

Vaughn
Altera

 

[Nahum Barnea]

tushitjain@yahoo.com (tushit) wrote in message news:<ec6aab0.0404262123.545dc255@posting.google.com>...

Hi,
I am using QuartusII 3.0. I setup a tsu requirement on some input pins
and quartus did a P&R and said it could not meet the tsu by 0.5ns on
only one of the paths. So I relaxed my tsu by about 1ns on all pins
and did an incremental fitting. Now Quartus came back and said it
could not meet timing on about 15 paths by 1.5ns. Why is this? Is
there anyway of adding more predictibility in the P&R of Quartus?
Thanks & regards
tushit

What was the violation over the 0.5 ns path ?
If the violation was less than 0.5 ns and you realy need 1 ns setup
then you can ignore the report .

Another idea:
instead of relaxing the constraints -> press them even further.
Ofcourse the report will say that more paths failed the 0.3 ns setup
constraint, but you might just find that all path met 0.5 ns setup.

Bye,
NAHUM