SKILL for DEF importing

[trisha.woods]

Hi All,
I need to import some DEF files into virtuoso. I want to automate
this process using SKILL. Can someone guide me to write the skill code
(or commands) to do the following things:

1. Import DEF
2. Convert all the abstract views to layout views
3. Remove the (outer) PR boundary of the design
4. Remove the boundary layer that surrounds each "row".

Is there any way to directly open the imported DEF (after all the
abstract views are replaced by layout views) in virtuoso instead of
virtuoso-preview. I mean, how can I open the layout in virtuoso (not
virtuoso-preview) when I click on the layout?

Thanks
-Trisha

 

1. Import DEF
On IC446, use Skill function gcireadCellViewDEF.

On IC50, use Skill function ldtrDefRead.
You could contact Cadence AE to get its full documentation.

2. Convert all the abstract views to layout views
Use Skill code to open layout, remove

some layout properties, and then change each sub view
into layout (inst~>viewName = "layout").

3. Remove the (outer) PR boundary of the design
This is easy... Find the prBoundary and delete the shape.

PS: Why do you need to do this?

4. Remove the boundary layer that surrounds each "row".
Same as No.3.

Is there any way to directly open the imported DEF (after all the
abstract views are replaced by layout views) in virtuoso instead of
virtuoso-preview. I mean, how can I open the layout in virtuoso (not
virtuoso-preview) when I click on the layout?
Opus use Preview when it recognizes some layout properties....

After removing these properties (such as maskLayoutSubType
and viewSubType), Opus will then use Virtuoso directly.

thanks,
ronald

 

[trisha.woods]

Actually I wrote a piece of code that processes the DEF of the entire
chip and creates a new DEF that only contains the std.cells, nets and
pins corresponding to a specific logic path (whose components are
defined in a seperate file). So, when I open the new layout (of this
specific path) I don't want the chip-boundary, rows etc. that
identifies the whose chip's layout.

The overall goal of this exercise is to isolate the layout-components
of a specific logic path from the entire chip's layout. I just wanted
to automate the DEF import part.

Thanks for your comments.
Trisha