size specification in size constant

[sandeep]

Hi
Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
I donot know my complain is valid or not but it is stupid thing. I
donot want to use `define construct instead my pref is parameter
construct.
Is there any way I can use parameter and write temp = {parameter'd28}
Regards

 

[Robert Miles]

"sandeep" <sandeepkumar.sah@gmail.com> wrote in message
news:b189510a-2767-431a-bb99-019fcce03f1e@n1g2000prb.googlegroups.com...

Hi
Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
I donot know my complain is valid or not but it is stupid thing. I
donot want to use `define construct instead my pref is parameter
construct.
Is there any way I can use parameter and write temp = {parameter'd28}
Regards
..

Constants are seldom called temp, so you might want to see if it helps if
you give it some other name instead.

 

[Rock]

On 11ÔÂ5ČŐ, ĎÂÎç1Ęą24ˇÖ, sandeep <sandeepkumar....@gmail.com> wrote:

Hi
Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
I donot know my complain is valid or not but it is stupid thing. I
donot want to use `define construct instead my pref is parameter
construct.
Is there any way I can use parameter and write temp = {parameter'd28}
Regards

The Verilog Spec just defines that we can use unsigned none zero
number as the SIZE.

 

[gabor]

On Nov 5, 12:24 am, sandeep <sandeepkumar....@gmail.com> wrote:

Hi
Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
I donot know my complain is valid or not but it is stupid thing. I
donot want to use `define construct instead my pref is parameter
construct.
Is there any way I can use parameter and write temp = {parameter'd28}
Regards

Deja Vu

Look for the thread:

Parameterised width assignments

in this newsgroup from May of last year.

 

[Jonathan Bromley]

On Tue, 4 Nov 2008 21:24:22 -0800 (PST), sandeep wrote:

Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
I donot know my complain is valid or not but it is stupid thing. I
donot want to use `define construct instead my pref is parameter
construct.
Is there any way I can use parameter and write temp = {parameter'd28}

Since Verilog-2001 it has been legal to size parameters explicitly.

parameter SIZE = 10;
parameter [SIZE-1:0] temp = 28;

Now you know for sure that temp is exactly SIZE bits wide,
and you can use it in concatenations etc.

As others have said, the bit-wdith in sized numbers like 8'b1 must
be a simple literal number, and cannot be a parameter. For some
constants it's possible to use replication:

parameter temp = {SIZE{1'b0}};

However, I would question why you ever need to do this. What
will you do with the sized constant? As soon as you copy it
into some other variable, it takes on the size of the target
variable:

parameter SIZE = 10;
parameter n = 28; // there is no need for this to be 10 bits wide
reg [SIZE-1:0] target;

initial begin
...
target = n; // this is legal even though "n" is 32 bits
...

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

On Nov 5, 12:24 am, sandeep <sandeepkumar....@gmail.com> wrote:

Hi
Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
Is there any way I can use parameter and write temp = {parameter'd28}

Not directly, no.

A sized constant is a single entity that represents a simple constant,
and has a specific syntax. It is not an expression, and the 'd is not
an operator that combines two arbitrary expressions. It is composed
of several lexical tokens, which can be separated by white space and
can be independently macro-substituted, but these tokens are not
expressions.

As an analogy, consider the syntax of a real constant (such as
1.5e3). That has 3 numeric fields in it, but you cannot replace those
with expressions either. You cannot use ONE.FIVEeTHREE to set the
integer part, fractional part and exponent from three different
parameters. That probably seems reasonable to you because you have
more experience with this notation. If not, consider the simpler case
of the integer constant 15. If you have parameters ONE=1 and FIVE=5,
you cannot use ONE FIVE to represent the constant 15. The closest you
can get is to use ONE*10+FIVE.

If you want to build a constant value from expressions, you will have
to do it with operators. One ugly way to do this one would be
{{(TEN-5){1'b0}}, 5'd28}.

But I have to ask why you are trying to do this anyway? Why do you
care what the width of the constant is? The "28" part is fixed, and
you know it requires at least 5 bits. You can just use 5'd28. If you
use it in a context where you need something wider, the Verilog rules
for implicit width conversions will take care of extending it for
you. That is what they are for, to avoid having to worry about this
kind of thing.

If you have tools that warn about width mismatches for this, then they
are just being annoying and unreasonable. If you just use 28 (which
is 32 bits wide) and they complain about truncation to 10 bits, that
isn't quite as unreasonable, though they could stand to be smarter and
recognize that they are just truncating zeroes. If you use 5'd28 and
they complain about truncation to less than 5 bits, you need to look
closer.

 

[Glen Herrmannsfeldt]

sandeep wrote:

Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
I donot know my complain is valid or not but it is stupid thing. I
donot want to use `define construct instead my pref is parameter
construct.
Is there any way I can use parameter and write temp = {parameter'd28}

You might be able to use the C preprocessor with verilog. I do wonder
about the apostrophes, though. I believe it is pretty rare, though.

-- glen

 

[sandeep]

On Nov 7, 10:35 am, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

sandeep wrote:
Consider following size constant -- "temp = 10'd28".
Now I want to replace 10 with parameter TEN = 10;
i.e temp = TEN'd28.
But compiler is giving error for above expression. It is allowing me
to use `define TEN 10
and `TEN'd28.
I donot know my complain is valid or not but it is stupid thing. I
donot want to use `define construct instead my pref is parameter
construct.
Is there any way I can use parameter and write temp = {parameter'd28}

You might be able to use the C preprocessor with verilog.  I do wonder
about the apostrophes, though.   I believe it is pretty rare, though.

-- glen

Hi Everyone
Thanks for replies. Actually i write verilog code for modem and i have
to write lots of code like
signal_a <= signal_a + 1;
signal_b <= signal_b + 7;
signal_c <= signal_c + 15;
etc...

Synthesis tool are not creating any problem but linting tools generate
lots of warning about
size mismatch. So i thought i will write integer constant in sized
constant format.
but then i start getting trouble whenever i change bit width of
signal_a/_b_c.. ..
Finally i think it is better to write like unsized constant and donot
care about lint warning.
signal_a <= signal_a + 'd5;
signal_b <= signal_b + 'd8;
etc..
regards