Size and Type of Parameters

[Russell Fredrickson]

Since, for now, I have to wait for more general support of typed and sized
parameters parts of Verilog 2001, I was wondering if anyone could explain
what the rules for what type and size a parameter is for Verilog 1995?

The current problem that drives the above question is that I want to have a
parameter that I want to be more than the seemingly 32-bit default size
(64-bits actually would be nice). I have tried assigning a 64-bit value to
the parameter by default to see if I would pick up on the bit-width as
follows:

parameter FOO = 64'b0;

but that didn't seem to move it to larger than 32-bits.

So am I stuck until my simulator supports these features, or is there a
way around this?

Thanks,
Russell

 

[Stephen Williams]

Russell Fredrickson wrote:

Since, for now, I have to wait for more general support of typed and sized
parameters parts of Verilog 2001, I was wondering if anyone could explain
what the rules for what type and size a parameter is for Verilog 1995?

The current problem that drives the above question is that I want to have a
parameter that I want to be more than the seemingly 32-bit default size
(64-bits actually would be nice). I have tried assigning a 64-bit value to
the parameter by default to see if I would pick up on the bit-width as
follows:

parameter FOO = 64'b0;

but that didn't seem to move it to larger than 32-bits.

So am I stuck until my simulator supports these features, or is there a
way around this?

Thanks,
Russell

Icarus Verilog shouldn't have this constraint. It never had a
magical 32bit boundary. The standard allowed truncating constant
expressions to 32bits, but never required it.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Rudolf Usselmann]

"Russell Fredrickson" <russell_fredrickson@hp.com> wrote in message news:<bj8fqp$see$1@news.vcd.hp.com>...

Since, for now, I have to wait for more general support of typed and sized
parameters parts of Verilog 2001, I was wondering if anyone could explain
what the rules for what type and size a parameter is for Verilog 1995?

The current problem that drives the above question is that I want to have a
parameter that I want to be more than the seemingly 32-bit default size
(64-bits actually would be nice). I have tried assigning a 64-bit value to
the parameter by default to see if I would pick up on the bit-width as
follows:

parameter FOO = 64'b0;

but that didn't seem to move it to larger than 32-bits.

So am I stuck until my simulator supports these features, or is there a
way around this?

Thanks,
Russell

Does your simulator support explicit width specifications
for parameters ?

e.g.
parameter [63:0] foo = 64'h0;

Can you tell us what simulator you are using ?

Regards,
rudi
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[Russell Fredrickson]

Does your simulator support explicit width specifications
for parameters ?

e.g.
parameter [63:0] foo = 64'h0;

Can you tell us what simulator you are using ?

Regards,
rudi

The simulator is NCVerilog and no it does no support sized parameters yet (a
Verilog 2001 enhancement). I may just talk to Cadence about it -- but I was
wondering if anyone else had found a way around this in this forum.

Thanks,
Russell

 

[Steven Sharp]

"Russell Fredrickson" <russell_fredrickson@hp.com> wrote in message news:<bj8fqp$see$1@news.vcd.hp.com>...

Since, for now, I have to wait for more general support of typed and sized
parameters parts of Verilog 2001, I was wondering if anyone could explain
what the rules for what type and size a parameter is for Verilog 1995?

It is the size and type of whatever constant expression ends up being
used to set its value.

The current problem that drives the above question is that I want to have a
parameter that I want to be more than the seemingly 32-bit default size
(64-bits actually would be nice). I have tried assigning a 64-bit value to
the parameter by default to see if I would pick up on the bit-width as
follows:

parameter FOO = 64'b0;

but that didn't seem to move it to larger than 32-bits.

Such a declaration would cause the parameter to be a 64-bit zero, as
long as this declaration actually ends up setting the parameter value.

I would guess that you are overriding this parameter value at instantiation
or with a defparam, using a 32-bit value. As soon as you do this, the
parameter becomes 32 bits in size, matching the value actually assigned.
If you used a 100-bit value, the parameter would become 100 bits in size,
and if you used a real value, the parameter would become real. The
original declaration doesn't determine the type of the parameter any
more permanently than it determines its value.

So am I stuck until my simulator supports these features, or is there a
way around this?

You can override it with a 64-bit value. If you want to be able to
declare it to be a particular type, no matter what it is overridden with,
you will need the Verilog-2001 typed parameters.

 

[Russell Fredrickson]

Thanks for the reply -- it seems to work now -- before posting I actaully
tried setting the parameter value I was assigning the parameter to in the
instantiation to a 64 bit number and it seemed to not work at the time. So
I thought I had tried that -- but I probably forgot to save a buffer before
running one of the simulation iterations when I was trying to get it to work
right.

Thanks,
Russell

"Steven Sharp" <sharp@cadence.com> wrote in message
news:3a8e124e.0309051421.71ba6727@posting.google.com...

"Russell Fredrickson" <russell_fredrickson@hp.com> wrote in message
news:<bj8fqp$see$1@news.vcd.hp.com>...
Since, for now, I have to wait for more general support of typed and
sized
parameters parts of Verilog 2001, I was wondering if anyone could
explain
what the rules for what type and size a parameter is for Verilog 1995?

It is the size and type of whatever constant expression ends up being
used to set its value.

The current problem that drives the above question is that I want to
have a
parameter that I want to be more than the seemingly 32-bit default size
(64-bits actually would be nice). I have tried assigning a 64-bit value
to
the parameter by default to see if I would pick up on the bit-width as
follows:

parameter FOO = 64'b0;

but that didn't seem to move it to larger than 32-bits.

Such a declaration would cause the parameter to be a 64-bit zero, as
long as this declaration actually ends up setting the parameter value.

I would guess that you are overriding this parameter value at
instantiation
or with a defparam, using a 32-bit value. As soon as you do this, the
parameter becomes 32 bits in size, matching the value actually assigned.
If you used a 100-bit value, the parameter would become 100 bits in size,
and if you used a real value, the parameter would become real. The
original declaration doesn't determine the type of the parameter any
more permanently than it determines its value.

So am I stuck until my simulator supports these features, or is
there a
way around this?

You can override it with a 64-bit value. If you want to be able to
declare it to be a particular type, no matter what it is overridden with,
you will need the Verilog-2001 typed parameters.