R
rekz
Guest
I am not sure if this is the right place to ask but since I am
implementing this in verilog then I'll go ask.
I am implementing a single cycle datapath to support for the MIPS
instruction architecture. A few of the instructions I will be doing is
mfhi, mflo, mthi, mtlo.
And also several loads/stores, such as lw, sw, lh, sh, sb, lb.
For the first 4 instructions, I am having difficulty of figuring out
where I should put the hi and lo register... is it inside my register
file? How do people usually do this?
For the lh, lb... I was thinking to add more control signals to the
data memory... so therefore everytime it tries to load it will check
if it's loading a byte or loading half word or a word otherwise.
Is this the correct and usual approach?
Sorry if this is the wrong place to ask, if it does, could someone
point me to the right place to ask for such computer architecture
questions
implementing this in verilog then I'll go ask.
I am implementing a single cycle datapath to support for the MIPS
instruction architecture. A few of the instructions I will be doing is
mfhi, mflo, mthi, mtlo.
And also several loads/stores, such as lw, sw, lh, sh, sb, lb.
For the first 4 instructions, I am having difficulty of figuring out
where I should put the hi and lo register... is it inside my register
file? How do people usually do this?
For the lh, lb... I was thinking to add more control signals to the
data memory... so therefore everytime it tries to load it will check
if it's loading a byte or loading half word or a word otherwise.
Is this the correct and usual approach?
Sorry if this is the wrong place to ask, if it does, could someone
point me to the right place to ask for such computer architecture
questions