Single byte addressable, multiple byte readout.

[Andreas]

Hi!

I'm looking for a memory system that allows the user to address a
single byte but then read out a longer chunk of data (in one clk),
lets say 4 words. If "-" represents one byte to read out and "----"
represents 4 bytes, the readout may be like this: addr=2
+--------+
| ---- |
| |
+--------+

It is hard (impossible?) to create this kind of memory since it
sometimes would need the use of two active bit-lines simountaneously.
For example addr=6
(the area represents the physical memory)
+--------+
| --|
|-- |
+--------+

Have anyone seen any memory and memory controller that is able to do
this?

One method is to divide the memory in banks, and then multiplex the
read out to its specific position, but that calls for a lot of
multiplesers when the readout gets bigger than 4 bytes, and the
addressing of the memory banks gets very complex. I need also a
systems that can handle 8,12,16... bytes readout, but still be single
byte addressable.

+----+ +----+
| 4 | | 4--|
|-- | | |
+----+ +----+
__|_______|__
\ mux /
-----------
| 4 byte

best regards,
Andreas

 

[Jonathan Bromley]

On 4 May 2004 04:15:50 -0700, d99alu@efd.lth.se (Andreas) wrote:

Hi!

I'm looking for a memory system that allows the user to address a
single byte but then read out a longer chunk of data (in one clk),
lets say 4 words. If "-" represents one byte to read out and "----"
represents 4 bytes, the readout may be like this: addr=2
+--------+
| ---- |
| |
+--------+

It is hard (impossible?) to create this kind of memory since it
sometimes would need the use of two active bit-lines simountaneously.
For example addr=6
(the area represents the physical memory)
+--------+
| --|
|-- |
+--------+

Have anyone seen any memory and memory controller that is able to do
this?

Many 32-bit CPUs can do "unaligned word addressing" like this.
Of course, it requires 2 separate accesses if the memory is
organised as the wide words.

One method is to divide the memory in banks, and then multiplex the
read out to its specific position, but that calls for a lot of
multiplesers when the readout gets bigger than 4 bytes

Agreed.

addressing of the memory banks gets very complex.

Not really - the address into each bank is either

base_address div word_size

or

(base_address div word_size) + 1

I need also a
systems that can handle 8,12,16... bytes readout

Is it *essential* to have unaliged transfer?

but still be single
byte addressable.

I don't see the byte addressing as a problem. If you
can do the unaligned access, then single-byte access
is trivial - choose the byte (with your mux) on read,
and on write you send the same data to all banks and
do a write-enable only on the chosen bank.

cheers
--
Jonathan Bromley, Consultant

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