sin3 filter for delta-sigma

[John Larkin]

If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

 

[Lasse Langwadt Christense]

tirsdag den 10. september 2019 kl. 22.00.29 UTC+2 skrev John Larkin:

If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

https://dspguru.com/files/cic.pdf

 

[John Larkin]

On Tue, 10 Sep 2019 13:00:19 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

This is a nice chip,

https://www.analog.com/media/en/technical-documentation/data-sheets/ADuM7703.pdf

but figs 25 and 31 sure don't help.

 

[Michael Kellett]

On 10/09/2019 21:00, John Larkin wrote:

If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

Here's a paper from Microsemi (1st hit on Google for "sinc3 filter
implementation")

UG0733
User Guide
Sinc3 Filter v4.2

It does show how the two clocks work.


https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwjKjduqrcjkAhVkqnEKHRemC1MQFjAAegQIAxAC&url=https%3A%2F%2Fwww.microsemi.com%2Fdocument-portal%2Fdoc_download%2F136388-ug0733-sinc3-filter-v4-2-user-guide&usg=AOvVaw3rRLe4bpnWgxjO7uaGOPdu


MK

---
This email has been checked for viruses by AVG.
https://www.avg.com

 

[Michael Kellett]

On 11/09/2019 09:35, Michael Kellett wrote:

On 10/09/2019 21:00, John Larkin wrote:


If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.



Here's a paper from Microsemi (1st hit on Google for "sinc3 filter
implementation")

UG0733
User Guide
Sinc3 Filter v4.2

It does show how the two clocks work.


https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwjKjduqrcjkAhVkqnEKHRemC1MQFjAAegQIAxAC&url=https%3A%2F%2Fwww.microsemi.com%2Fdocument-portal%2Fdoc_download%2F136388-ug0733-sinc3-filter-v4-2-user-guide&usg=AOvVaw3rRLe4bpnWgxjO7uaGOPdu



MK

---
This email has been checked for viruses by AVG.
https://www.avg.com

More and better descriptions here:

TI sbaa094

http://www.ti.com/lit/an/sbaa094/sbaa094.pdf

MK

 

[Johann Klammer]

On 09/10/2019 10:00 PM, John Larkin wrote:

If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

Careful with the sidelobes. they all alias into the passband, so
those filters look better than they actually are.

 

On Wed, 11 Sep 2019 16:11:00 +0200, Johann Klammer
<klammerj@NOSPAM.a1.net> wrote:

On 09/10/2019 10:00 PM, John Larkin wrote:


If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.



Careful with the sidelobes. they all alias into the passband, so
those filters look better than they actually are.

I need to send the d-s signals into my FPGA, then do the sinc3
filtering, then the signal math. But I also want to send the analog
signals out to some monitor BNC connectors on the front panel. Rather
than coming back out of the FPGA with DACs, why not analog filter the
delta-sigma stream outside the FPGA? That wouldn't have the sidelobes.
The lowpass would just have to cut off sorta below the noise shaping
region of the modulator, and only needs to look good on a scope, so
that shouldn't be difficult.

One might even imagine recovering the delta-sigma signal with a good
analog filter, then digitizing it into the FPGA. Or using some sort of
digital lowpass filter in the FPGA that's not sinc3.

Actually, my signals will be mostly low frequency sine waves, or
chopped-up low frequency sines, so aliasing into the upper lobes of
the filter wouldn't be a big problem.

 

[Lasse Langwadt Christense]

onsdag den 11. september 2019 kl. 16.52.59 UTC+2 skrev jla...@highlandsniptechnology.com:

On Wed, 11 Sep 2019 16:11:00 +0200, Johann Klammer
klammerj@NOSPAM.a1.net> wrote:

On 09/10/2019 10:00 PM, John Larkin wrote:


If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.



Careful with the sidelobes. they all alias into the passband, so
those filters look better than they actually are.

I need to send the d-s signals into my FPGA, then do the sinc3
filtering, then the signal math. But I also want to send the analog
signals out to some monitor BNC connectors on the front panel. Rather
than coming back out of the FPGA with DACs, why not analog filter the
delta-sigma stream outside the FPGA? That wouldn't have the sidelobes.
The lowpass would just have to cut off sorta below the noise shaping
region of the modulator, and only needs to look good on a scope, so
that shouldn't be difficult.

One might even imagine recovering the delta-sigma signal with a good
analog filter, then digitizing it into the FPGA. Or using some sort of
digital lowpass filter in the FPGA that's not sinc3.

Actually, my signals will be mostly low frequency sine waves, or
chopped-up low frequency sines, so aliasing into the upper lobes of
the filter wouldn't be a big problem.

if you want analog out you might as well just lowpass the stream directly

silly to go analog and then back to digital, if you have room in the FPGA you
can use a "proper" filter, the advantage of a CIC sinc3 filter is that it only
needs few adders and registers

 

On Wed, 11 Sep 2019 09:11:07 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

onsdag den 11. september 2019 kl. 16.52.59 UTC+2 skrev jla...@highlandsniptechnology.com:
On Wed, 11 Sep 2019 16:11:00 +0200, Johann Klammer
klammerj@NOSPAM.a1.net> wrote:

On 09/10/2019 10:00 PM, John Larkin wrote:


If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.



Careful with the sidelobes. they all alias into the passband, so
those filters look better than they actually are.

I need to send the d-s signals into my FPGA, then do the sinc3
filtering, then the signal math. But I also want to send the analog
signals out to some monitor BNC connectors on the front panel. Rather
than coming back out of the FPGA with DACs, why not analog filter the
delta-sigma stream outside the FPGA? That wouldn't have the sidelobes.
The lowpass would just have to cut off sorta below the noise shaping
region of the modulator, and only needs to look good on a scope, so
that shouldn't be difficult.

One might even imagine recovering the delta-sigma signal with a good
analog filter, then digitizing it into the FPGA. Or using some sort of
digital lowpass filter in the FPGA that's not sinc3.

Actually, my signals will be mostly low frequency sine waves, or
chopped-up low frequency sines, so aliasing into the upper lobes of
the filter wouldn't be a big problem.

if you want analog out you might as well just lowpass the stream directly

Exactly. A dumb 3rd order sallen-key should do it.

silly to go analog and then back to digital, if you have room in the FPGA you
can use a "proper" filter, the advantage of a CIC sinc3 filter is that it only
needs few adders and registers

Right, sinc3 might not be the best filter. We'll have gobs of
resources in the FPGA.

Maybe I'll Spice the delta-sigma modulator just for fun, and play with
analog filters. But it might take ages to run.

 

[Rick C]

On Wednesday, September 11, 2019 at 12:27:19 PM UTC-4, jla...@highlandsniptechnology.com wrote:

On Wed, 11 Sep 2019 09:11:07 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

onsdag den 11. september 2019 kl. 16.52.59 UTC+2 skrev jla...@highlandsniptechnology.com:
On Wed, 11 Sep 2019 16:11:00 +0200, Johann Klammer
klammerj@NOSPAM.a1.net> wrote:

On 09/10/2019 10:00 PM, John Larkin wrote:


If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.



Careful with the sidelobes. they all alias into the passband, so
those filters look better than they actually are.

I need to send the d-s signals into my FPGA, then do the sinc3
filtering, then the signal math. But I also want to send the analog
signals out to some monitor BNC connectors on the front panel. Rather
than coming back out of the FPGA with DACs, why not analog filter the
delta-sigma stream outside the FPGA? That wouldn't have the sidelobes.
The lowpass would just have to cut off sorta below the noise shaping
region of the modulator, and only needs to look good on a scope, so
that shouldn't be difficult.

One might even imagine recovering the delta-sigma signal with a good
analog filter, then digitizing it into the FPGA. Or using some sort of
digital lowpass filter in the FPGA that's not sinc3.

Actually, my signals will be mostly low frequency sine waves, or
chopped-up low frequency sines, so aliasing into the upper lobes of
the filter wouldn't be a big problem.

if you want analog out you might as well just lowpass the stream directly

Exactly. A dumb 3rd order sallen-key should do it.


silly to go analog and then back to digital, if you have room in the FPGA you
can use a "proper" filter, the advantage of a CIC sinc3 filter is that it only
needs few adders and registers

Right, sinc3 might not be the best filter. We'll have gobs of
resources in the FPGA.

Maybe I'll Spice the delta-sigma modulator just for fun, and play with
analog filters. But it might take ages to run.

Run the delta-sigma filter in a VHDL simulation. It's a simple circuit and will run quickly. It's not hard to do analog filters in VHDL either. You just have to write a few equations and have them evaluated with an adequate resolution. I've written simple RC filters this way.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Tuesday, September 10, 2019 at 4:00:29 PM UTC-4, John Larkin wrote:

If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd build a
sinc3 filter into an FPGA to make the data stream into, say, 16 bit
parallel form. The d-s converter would run at maybe 20 MHz, and I
could probably get 16-bit digitizing with about 150 KHz equivalent
bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an output
sample rate? I see appnotes that specify output sample rate as
Fckl/OSR, where OSR is the oversample ratio, maybe 32 for me. Why
isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which is
OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

I'm not sure what you are missing. The sigma-delta stage produces a 1 bit stream at your oversample rate. The filtering decimates and produces a wider word with more resolution. You can pick off samples every 50 ns, but they won't be 16 bits. The way they get the wider word is to decimate in the filter combining input samples to provide more resolution in the lower sample rate output.

If you'd like to filter without decimating, you will end up with a smaller bandwidth but no additional resolution.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Jeroen Belleman]

Rick C wrote:

On Tuesday, September 10, 2019 at 4:00:29 PM UTC-4, John Larkin
wrote:
If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd
build a sinc3 filter into an FPGA to make the data stream into,
say, 16 bit parallel form. The d-s converter would run at maybe
20 MHz, and I could probably get 16-bit digitizing with about
150 KHz equivalent bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an
output sample rate? I see appnotes that specify output sample
rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32
for me. Why isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which
is OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

I'm not sure what you are missing. The sigma-delta stage produces
a 1 bit stream at your oversample rate. The filtering decimates
and produces a wider word with more resolution. You can pick off
samples every 50 ns, but they won't be 16 bits. The way they get
the wider word is to decimate in the filter combining input
samples to provide more resolution in the lower sample rate
output.

If you'd like to filter without decimating, you will end up with a
smaller bandwidth but no additional resolution.

The filtering is necessary, but the decimation is optional.

Jeroen Belleman

 

[Rick C]

On Thursday, September 12, 2019 at 4:15:21 AM UTC-4, Jeroen Belleman wrote:

Rick C wrote:
On Tuesday, September 10, 2019 at 4:00:29 PM UTC-4, John Larkin
wrote:
If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd
build a sinc3 filter into an FPGA to make the data stream into,
say, 16 bit parallel form. The d-s converter would run at maybe
20 MHz, and I could probably get 16-bit digitizing with about
150 KHz equivalent bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an
output sample rate? I see appnotes that specify output sample
rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32
for me. Why isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which
is OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

I'm not sure what you are missing. The sigma-delta stage produces
a 1 bit stream at your oversample rate. The filtering decimates
and produces a wider word with more resolution. You can pick off
samples every 50 ns, but they won't be 16 bits. The way they get
the wider word is to decimate in the filter combining input
samples to provide more resolution in the lower sample rate
output.

If you'd like to filter without decimating, you will end up with a
smaller bandwidth but no additional resolution.


The filtering is necessary, but the decimation is optional.

Yeah, I suppose without the decimation you would get the additional resolution, but for a narrower bandwidth signal which is vastly oversampled. So yeah, the decimation is not required.

I guess I'm used to thinking the decimation is part of the filter. In reality it isn't. Thanks,

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

On Thu, 12 Sep 2019 10:15:16 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

Rick C wrote:
On Tuesday, September 10, 2019 at 4:00:29 PM UTC-4, John Larkin
wrote:
If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd
build a sinc3 filter into an FPGA to make the data stream into,
say, 16 bit parallel form. The d-s converter would run at maybe
20 MHz, and I could probably get 16-bit digitizing with about
150 KHz equivalent bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an
output sample rate? I see appnotes that specify output sample
rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32
for me. Why isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which
is OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

I'm not sure what you are missing. The sigma-delta stage produces
a 1 bit stream at your oversample rate. The filtering decimates
and produces a wider word with more resolution. You can pick off
samples every 50 ns, but they won't be 16 bits. The way they get
the wider word is to decimate in the filter combining input
samples to provide more resolution in the lower sample rate
output.

If you'd like to filter without decimating, you will end up with a
smaller bandwidth but no additional resolution.


The filtering is necessary, but the decimation is optional.

Jeroen Belleman

Right. A classic FIR filter has one input per clock and one output per
same clock.

I may want to differentiate one of my signals, and would prefer that
the filter output be as continuous as possible. Decimation makes big
steps.

I have Verilog for a sinc3 filter. I'll have one of my FPGA kids
figure out what it actually does, and why it decimates.

 

[Rick C]

On Thursday, September 12, 2019 at 10:12:25 AM UTC-4, jla...@highlandsniptechnology.com wrote:

On Thu, 12 Sep 2019 10:15:16 +0200, Jeroen Belleman
jeroen@nospam.please> wrote:

Rick C wrote:
On Tuesday, September 10, 2019 at 4:00:29 PM UTC-4, John Larkin
wrote:
If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd
build a sinc3 filter into an FPGA to make the data stream into,
say, 16 bit parallel form. The d-s converter would run at maybe
20 MHz, and I could probably get 16-bit digitizing with about
150 KHz equivalent bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an
output sample rate? I see appnotes that specify output sample
rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32
for me. Why isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which
is OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

I'm not sure what you are missing. The sigma-delta stage produces
a 1 bit stream at your oversample rate. The filtering decimates
and produces a wider word with more resolution. You can pick off
samples every 50 ns, but they won't be 16 bits. The way they get
the wider word is to decimate in the filter combining input
samples to provide more resolution in the lower sample rate
output.

If you'd like to filter without decimating, you will end up with a
smaller bandwidth but no additional resolution.


The filtering is necessary, but the decimation is optional.

Jeroen Belleman

Right. A classic FIR filter has one input per clock and one output per
same clock.

I may want to differentiate one of my signals, and would prefer that
the filter output be as continuous as possible. Decimation makes big
steps.

I have Verilog for a sinc3 filter. I'll have one of my FPGA kids
figure out what it actually does, and why it decimates.

It decimates because the higher sample rate is redundant. If the filter uses CIC it will need to be rewritten completely to remove the decimation. CIC is often followed by a FIR filter which sharpens up the band edges. The CIC filter will need to be replaced with a massive FIR with no actual multiplies (in fact it seems to simplify to a box car filter) followed by a full speed version of the final FIR filter full of multiplies from the many, many taps (original number of taps times the decimation rate).

If the differentiation does not require the final filter and that is only needed for the decimated output, the FIR can be implemented as a poly phase decimating filter which will be the same complexity as the existing FIR filter.

Another thought is to leave the filter as is and reconstruct the higher sample rate by interpolation. You may not need the full 20 MHz sample rate, so you can set it to what you want.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christense]

torsdag den 12. september 2019 kl. 16.12.25 UTC+2 skrev jla...@highlandsniptechnology.com:

On Thu, 12 Sep 2019 10:15:16 +0200, Jeroen Belleman
jeroen@nospam.please> wrote:

Rick C wrote:
On Tuesday, September 10, 2019 at 4:00:29 PM UTC-4, John Larkin
wrote:
If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd
build a sinc3 filter into an FPGA to make the data stream into,
say, 16 bit parallel form. The d-s converter would run at maybe
20 MHz, and I could probably get 16-bit digitizing with about
150 KHz equivalent bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an
output sample rate? I see appnotes that specify output sample
rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32
for me. Why isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which
is OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

I'm not sure what you are missing. The sigma-delta stage produces
a 1 bit stream at your oversample rate. The filtering decimates
and produces a wider word with more resolution. You can pick off
samples every 50 ns, but they won't be 16 bits. The way they get
the wider word is to decimate in the filter combining input
samples to provide more resolution in the lower sample rate
output.

If you'd like to filter without decimating, you will end up with a
smaller bandwidth but no additional resolution.


The filtering is necessary, but the decimation is optional.

Jeroen Belleman

Right. A classic FIR filter has one input per clock and one output per
same clock.

I may want to differentiate one of my signals, and would prefer that
the filter output be as continuous as possible. Decimation makes big
steps.

I have Verilog for a sinc3 filter. I'll have one of my FPGA kids
figure out what it actually does, and why it decimates.

it is a CIC filter, integrators followed by differentiators

https://www.dsprelated.com/blogimages/RickLyons/Multirate_Trans_Func_figure1.PNG

if you don't decimate before the differentiators you need OSR times more memory
in the differentiators

 

[Lasse Langwadt Christense]

torsdag den 12. september 2019 kl. 22.01.38 UTC+2 skrev Rick C:

Or it can be done with fewer adders by simply adding in the latest sample and subtracting out the oldest on each iteration.

yep, that is what it does in a clever way that avoids the long delay line
for "oldest"

 

[Rick C]

On Thursday, September 12, 2019 at 12:23:33 PM UTC-4, Lasse Langwadt Christensen wrote:

torsdag den 12. september 2019 kl. 16.12.25 UTC+2 skrev jla...@highlandsniptechnology.com:
On Thu, 12 Sep 2019 10:15:16 +0200, Jeroen Belleman
jeroen@nospam.please> wrote:

Rick C wrote:
On Tuesday, September 10, 2019 at 4:00:29 PM UTC-4, John Larkin
wrote:
If I use an isolated delta-sigma modulator, like a TI AMC1306 or
something, to pick off the signal on a current shunt, we'd
build a sinc3 filter into an FPGA to make the data stream into,
say, 16 bit parallel form. The d-s converter would run at maybe
20 MHz, and I could probably get 16-bit digitizing with about
150 KHz equivalent bandwidth.

If the sinc3 is (I think) essentially a FIR filter, is there an
output sample rate? I see appnotes that specify output sample
rate as Fckl/OSR, where OSR is the oversample ratio, maybe 32
for me. Why isn't new filtered data available every 50 ns?

20 MHz/32 is a "sample rate" out of the filter of 625 KHz, which
is OK, but why?

My fpga/signals guy is ooo, or I'd ask him.

I'm not sure what you are missing. The sigma-delta stage produces
a 1 bit stream at your oversample rate. The filtering decimates
and produces a wider word with more resolution. You can pick off
samples every 50 ns, but they won't be 16 bits. The way they get
the wider word is to decimate in the filter combining input
samples to provide more resolution in the lower sample rate
output.

If you'd like to filter without decimating, you will end up with a
smaller bandwidth but no additional resolution.


The filtering is necessary, but the decimation is optional.

Jeroen Belleman

Right. A classic FIR filter has one input per clock and one output per
same clock.

I may want to differentiate one of my signals, and would prefer that
the filter output be as continuous as possible. Decimation makes big
steps.

I have Verilog for a sinc3 filter. I'll have one of my FPGA kids
figure out what it actually does, and why it decimates.

it is a CIC filter, integrators followed by differentiators

https://www.dsprelated.com/blogimages/RickLyons/Multirate_Trans_Func_figure1.PNG

if you don't decimate before the differentiators you need OSR times more memory
in the differentiators

If you aren't decimating doesn't a CIC filter become a boxcar average? Yes, I see Wikipedia refers to the CIC as "an efficient implementation of a moving-average filter". So that is just N delay elements and N adders. Or it can be done with fewer adders by simply adding in the latest sample and subtracting out the oldest on each iteration.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Thursday, September 12, 2019 at 4:20:48 PM UTC-4, Lasse Langwadt Christensen wrote:

torsdag den 12. september 2019 kl. 22.01.38 UTC+2 skrev Rick C:


Or it can be done with fewer adders by simply adding in the latest sample and subtracting out the oldest on each iteration.


yep, that is what it does in a clever way that avoids the long delay line
for "oldest"

The delay line is there, it's just not so long and has adders as well. It's the decimation that allows it to be log2(N) long rather than N. Just like in a polyphase FIR filter it saves the calculations you won't be needing to produce a result. If you remove the decimation a polyphase FIR becomes a standard FIR calculated in sections.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

 

[Lasse Langwadt Christense]

torsdag den 12. september 2019 kl. 22.42.44 UTC+2 skrev Rick C:

On Thursday, September 12, 2019 at 4:20:48 PM UTC-4, Lasse Langwadt Christensen wrote:
torsdag den 12. september 2019 kl. 22.01.38 UTC+2 skrev Rick C:


Or it can be done with fewer adders by simply adding in the latest sample and subtracting out the oldest on each iteration.


yep, that is what it does in a clever way that avoids the long delay line
for "oldest"

The delay line is there, it's just not so long and has adders as well. It's the decimation that allows it to be log2(N) long rather than N. Just like in a polyphase FIR filter it saves the calculations you won't be needing to produce a result. If you remove the decimation a polyphase FIR becomes a standard FIR calculated in sections.

https://www.dsprelated.com/blogimages/RickLyons/Multirate_Trans_Func_figure1.PNG

with the rate change moved to before the combs the delays is one sample at the output rate instead of R samples at the input rate