Simulink/Active HDL Cosimulation

Hi,

I would like to simulate my VHDL design under Simulink.

I have read the information on the ALDEC web site but it's impossible
to set a time step under 1 ns !!!

I cannot simulate with time step under 1 ns !!

Simulink says :

Active-HDL sample period must be > 1ns (1e-9). Sample period must be in
range from 1ns to 1s !!!!

Thanks

 

Effectively, I've got the 6.2 version...

Thanks ...

 

I assume you are using Active-HDL 6.3 or earlier. Please try the new
Active-HDL 7.1. In this new version, both the Simulink and Matlab
interface has been greatly enhanced and simplified.

In the new version, you generate Simulink Block from Active-HDL in one
single step without setting parameters. You set parameters in Simulink
GUI once you open the cosimulation in Simulink.

The synchronization between the two tools are much enhanced and more
straitforward. There is no limitation on the "sampling period" for
Active-HDL. What is more, you can set Simulink sample period
independently - either explicitly like in ps, ns... or you can set it
relative to sample period that is is for Active-HDL.

Personally, I find the new interface much more easier to use and
obviously more capable.