simulation trouble

[Vandana]

Hi All,

I have included a snippet of my code below in which I have some
trouble.
When I simulate I find that the time does not advance.
If I remove the for i in 0 to 5 loop, then the time advances, but I
find that the UNIFORM call does not change the value of z. What am I
doing wrong here?

Thanks for your time.

Thanks,
Vandana


-----------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
----------------------------
...
...
----------

begin -- behav

latch : process is

variable seed1, seed2 : integer := 1;
variable z : real := 0.0;
variable k : integer;
variable ra_s,ca_s,ba_s,cra_s : integer := 0;

begin
loop

for i in 0 to 5 loop
-- wait until clk = '1';
UNIFORM(seed1 ,seed2,z);
--wait until clk = '1';
if (z < 1.0/3.0) then
write_en <= '1' ; read_en <= '0' ; refresh_en <= '1' ;
wait until clk = '1';
elsif (z > 1.0/3.0 and z < 2.0/3.0) then
write_en <= '0'; read_en <= '1'; refresh_en <=
'1';
wait until clk = '1';
else
for b in 0 to 2 loop
write_en <= '1'; read_en <= '1';
refresh_en <= '0';
for i in 0 to 7 loop -- 8 banks
cra <=
std_ulogic_vector(to_unsigned(i, cra'length));
wait until clk ='1';
end loop ;
end loop;
end if;
end loop;
end loop;
end process latch;

end behav;

 

[Mark McDougall]

Vandana wrote:

I have included a snippet of my code below in which I have some
trouble. When I simulate I find that the time does not advance. If I
remove the for i in 0 to 5 loop, then the time advances, but I find
that the UNIFORM call does not change the value of z. What am I doing
wrong here?

Just a guess, but IIRC the "wait until clk = '1'" lines are only woken on
a simulation event and if the clock is already '1', there's no event and
it'll wait forever...

If that's the case, you could, for example, add a "wait for 1 ns"
before/after each one...

Anyone confirm/refute?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Tricky]

-----------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
----------------------------
..
..
----------

begin  -- behav

  latch                                 : process is

  variable seed1, seed2                    : integer := 1;
  variable z                                       : real := 0.0;
  variable k                                       : integer;
  variable ra_s,ca_s,ba_s,cra_s         : integer := 0;

what are these extra variables for? you only use seed1, seed2 and z

begin
loop

Why have you got a stray "loop"? processes naturally loop

    for i in 0 to 5 loop
     -- wait until clk = '1';
        UNIFORM(seed1 ,seed2,z);
        --wait until clk = '1';
                if (z < 1.0/3.0) then
                        write_en <= '1' ; read_en <= '0' ;  refresh_en <= '1' ;

I assume all of these signals are active low? it may be better
practice (only from a personal pov) to name the signals n_refresh_en
to let others know their intention.

                        wait until clk = '1';
                elsif (z > 1.0/3.0 and z < 2.0/3.0) then
                        write_en <= '0'; read_en <= '1'; refresh_en <> '1';
                        wait until clk = '1';
                else

This case also catches when z = 1.0/3.0 (although it will probably
rarely happen).

                        for b in 0 to 2 loop
                                write_en <= '1'; read_en <= '1';
refresh_en <= '0';
                                for i in 0 to 7 loop   -- 8 banks
                                        cra <> std_ulogic_vector(to_unsigned(i, cra'length));
                                        wait until clk ='1';
                                end loop ;
                        end loop;
                end if;
           end loop;
end loop;

Remove this loop. If you want to halt this process, put a wait; at the
end

end process latch;

end behav;

Other than that, I dont know why its not working on your machine. I
took your code as is and it worked fine on modelsim. Are you sure
you've made a process that toggles the clock?