simulation problems

[Anuja]

I am trying to convert a Verilog file to VHDL.

Verilog File =>
module Reg2(Q, D, en, rst, clk);
parameter REGWIDTH = 2;
input clk, en, rst;
input [(REGWIDTH-1):0] D;
output [(REGWIDTH-1):0] Q;
reg [(REGWIDTH-1):0] Q_int;
assign Q = (rst == 0)? Q_int : 2'd0;
always @ (posedge clk)
begin
if (rst == 1)
Q_int <= 2'd0;
else if (en == 1)
Q_int <= D;
else
Q_int <= Q_int;
end
endmodule


VHDL File =>
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Reg2 IS
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END Reg2;

ARCHITECTURE behavioral OF Reg2 IS
-- register and constant declaration
SIGNAL Q_int : std_logic_vector(1 downto 0);
CONSTANT LO : std_logic := '0';
CONSTANT HI : std_logic := '1';

BEGIN

Q <= Q_int when (rst = LO) else "00";

one : PROCESS (clk)
BEGIN

IF (clk = HI and clk'event) THEN

IF (rst = HI) THEN
Q_int <= "00";
ELSIF (en = HI) THEN
Q_int <= D;
END IF;

END IF;

END PROCESS one;

END behavioral;


VHDL test bench =>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Reg2 is
-- testbench entity is ALWAYS EMPTY
END tb_Reg2;
ARCHITECTURE tb of tb_Reg2 is

-- temporary signals
SIGNAL clk_temp : std_logic := '0';
SIGNAL rst_temp, en_temp : std_logic := '0';
SIGNAL D_temp, Q_temp : std_logic_vector(1 downto 0):= "00";

-- component declaration
COMPONENT Reg2 is
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

BEGIN
UUT : Reg2
PORT MAP( clk => clk_temp,
rst => rst_temp,
en => en_temp,
D => D_temp,
Q => Q_temp
);

-- Passing values to inputs
clk_temp <= (not clk_temp) after 5 ns;

rst_temp <= '0' after 0 ns,'1' after 3 ns,'0' after 15
ns;

en_temp <= '1' after 5 ns,'0' after 11 ns,'1' after
18 ns,
'0' after 26 ns,'1' after 45 ns;

D_temp <= "11" after 4 ns, "10" after 16 ns,
"01" after 32 ns,"00" after 55 ns;

END tb; -- test bench ends


Whenever i am trying to simulate the test bench, the value of Q_int
and hence Q is always "00".
Please help

Anuja

 

[Ann]

On Dec 7, 4:34 pm, Anuja <thakkar.an...@gmail.com> wrote:

I am trying to convert a Verilog file to VHDL.

Verilog File =
module Reg2(Q, D, en, rst, clk);
parameter REGWIDTH = 2;
input clk, en, rst;
input [(REGWIDTH-1):0] D;
output [(REGWIDTH-1):0] Q;
reg [(REGWIDTH-1):0] Q_int;
assign Q = (rst == 0)? Q_int : 2'd0;
always @ (posedge clk)
begin
if (rst == 1)
Q_int <= 2'd0;
else if (en == 1)
Q_int <= D;
else
Q_int <= Q_int;
end
endmodule

VHDL File =
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Reg2 IS
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END Reg2;

ARCHITECTURE behavioral OF Reg2 IS
-- register and constant declaration
SIGNAL Q_int : std_logic_vector(1 downto 0);
CONSTANT LO : std_logic := '0';
CONSTANT HI : std_logic := '1';

BEGIN

Q <= Q_int when (rst = LO) else "00";

one : PROCESS (clk)
BEGIN

IF (clk = HI and clk'event) THEN

IF (rst = HI) THEN
Q_int <= "00";
ELSIF (en = HI) THEN
Q_int <= D;
END IF;

END IF;

END PROCESS one;

END behavioral;

VHDL test bench =
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Reg2 is
-- testbench entity is ALWAYS EMPTY
END tb_Reg2;
ARCHITECTURE tb of tb_Reg2 is

-- temporary signals
SIGNAL clk_temp : std_logic := '0';
SIGNAL rst_temp, en_temp : std_logic := '0';
SIGNAL D_temp, Q_temp : std_logic_vector(1 downto 0):= "00";

-- component declaration
COMPONENT Reg2 is
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

BEGIN
UUT : Reg2
PORT MAP( clk => clk_temp,
rst => rst_temp,
en => en_temp,
D => D_temp,
Q => Q_temp
);

-- Passing values to inputs
clk_temp <= (not clk_temp) after 5 ns;

rst_temp <= '0' after 0 ns,'1' after 3 ns,'0' after 15
ns;

en_temp <= '1' after 5 ns,'0' after 11 ns,'1' after
18 ns,
'0' after 26 ns,'1' after 45 ns;

D_temp <= "11" after 4 ns, "10" after 16 ns,
"01" after 32 ns,"00" after 55 ns;

END tb; -- test bench ends

Whenever i am trying to simulate the test bench, the value of Q_int
and hence Q is always "00".
Please help

Anuja

I FOUND THE SOLUTION. INSTEAD OF USING TEMPORARY SIGNAL Q_INT, I
DIRECTLY UPDATED THE VALUE OF OUTPUT Q. IT IS WORKING FINE NOW.