simulation problems

A

Ann

Guest
I am trying to convert a Verilog file to VHDL.

Verilog File =>
module Reg2(Q, D, en, rst, clk);
parameter REGWIDTH = 2;
input clk, en, rst;
input [(REGWIDTH-1):0] D;
output [(REGWIDTH-1):0] Q;
reg [(REGWIDTH-1):0] Q_int;
assign Q = (rst == 0)? Q_int : 2'd0;
always @ (posedge clk)
begin
if (rst == 1)
Q_int <= 2'd0;
else if (en == 1)
Q_int <= D;
else
Q_int <= Q_int;
end
endmodule


VHDL File =>
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Reg2 IS
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END Reg2;

ARCHITECTURE behavioral OF Reg2 IS
-- register and constant declaration
SIGNAL Q_int : std_logic_vector(1 downto 0);
CONSTANT LO : std_logic := '0';
CONSTANT HI : std_logic := '1';

BEGIN

Q <= Q_int when (rst = LO) else "00";

one : PROCESS (clk)
BEGIN

IF (clk = HI and clk'event) THEN

IF (rst = HI) THEN
Q_int <= "00";
ELSIF (en = HI) THEN
Q_int <= D;
END IF;

END IF;

END PROCESS one;

END behavioral;


VHDL test bench =>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Reg2 is
-- testbench entity is ALWAYS EMPTY
END tb_Reg2;
ARCHITECTURE tb of tb_Reg2 is

-- temporary signals
SIGNAL clk_temp : std_logic := '0';
SIGNAL rst_temp, en_temp : std_logic := '0';
SIGNAL D_temp, Q_temp : std_logic_vector(1 downto 0):= "00";

-- component declaration
COMPONENT Reg2 is
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

BEGIN
UUT : Reg2
PORT MAP( clk => clk_temp,
rst => rst_temp,
en => en_temp,
D => D_temp,
Q => Q_temp
);

-- Passing values to inputs
clk_temp <= (not clk_temp) after 5 ns;

rst_temp <= '0' after 0 ns,'1' after 3 ns,'0' after 15
ns;

en_temp <= '1' after 5 ns,'0' after 11 ns,'1' after
18 ns,
'0' after 26 ns,'1' after 45 ns;

D_temp <= "11" after 4 ns, "10" after 16 ns,
"01" after 32 ns,"00" after 55 ns;

END tb; -- test bench ends


Whenever i am trying to simulate the test bench, the value of Q_int
and hence Q is always "00". I dont know what is wrong. Do you have any
idea?

Ann
 
Ann wrote:
I am trying to convert a Verilog file to VHDL.

Verilog File =
module Reg2(Q, D, en, rst, clk);
parameter REGWIDTH = 2;
input clk, en, rst;
input [(REGWIDTH-1):0] D;
output [(REGWIDTH-1):0] Q;
reg [(REGWIDTH-1):0] Q_int;
assign Q = (rst == 0)? Q_int : 2'd0;
always @ (posedge clk)
begin
if (rst == 1)
Q_int <= 2'd0;
else if (en == 1)
Q_int <= D;
else
Q_int <= Q_int;
end
endmodule
Click to expand...
Lets put that on the viewer to start with.
http://home.comcast.net/~mike_treseler/Reg2.pdf

Hmmm. .. are you sure that's what you want?
I would prefer putting the register on the output.

-- Mike Treseler
 
On Fri, 7 Dec 2007 13:43:03 -0800 (PST), Ann <thakkar.anuja@gmail.com>
wrote:

I am trying to convert a Verilog file to VHDL.

Verilog File =
module Reg2(Q, D, en, rst, clk);
parameter REGWIDTH = 2;
input clk, en, rst;
input [(REGWIDTH-1):0] D;
output [(REGWIDTH-1):0] Q;
reg [(REGWIDTH-1):0] Q_int;
assign Q = (rst == 0)? Q_int : 2'd0;
always @ (posedge clk)
begin
if (rst == 1)
Q_int <= 2'd0;
else if (en == 1)
Q_int <= D;
else
Q_int <= Q_int;
end
endmodule

There is a synchronous reset control at the input of the register and
Click to expand...
a mux at the ouput of the register controlled by reset. You seem to
want an asynchronous reset register, it would be cleaner if you coded
it that way.

...
clk_temp <= (not clk_temp) after 5 ns;
Click to expand...
Does this really create a constantly toggling clock?
 
On Sat, 08 Dec 2007 10:50:32 -0800, Mike Treseler
<mike_treseler@comcast.net> wrote:

Ann wrote:
I am trying to convert a Verilog file to VHDL.

Verilog File =
module Reg2(Q, D, en, rst, clk);
parameter REGWIDTH = 2;
input clk, en, rst;
input [(REGWIDTH-1):0] D;
output [(REGWIDTH-1):0] Q;
reg [(REGWIDTH-1):0] Q_int;
assign Q = (rst == 0)? Q_int : 2'd0;
always @ (posedge clk)
begin
if (rst == 1)
Q_int <= 2'd0;
else if (en == 1)
Q_int <= D;
else
Q_int <= Q_int;
end
endmodule

Lets put that on the viewer to start with.
http://home.comcast.net/~mike_treseler/Reg2.pdf

Hmmm. .. are you sure that's what you want?
I would prefer putting the register on the output.
Click to expand...
Then you wouldn't get the async reset effect the code seems to be
going for. The mux at the output simulates that. It would be easier to
change the flop to async reset with
always @ (posedge rst, posedge clk)
begin
if (rst == 1)
....
 
Ann wrote:
I am trying to convert a Verilog file to VHDL.
....
Whenever i am trying to simulate the test bench, the value of Q_int
and hence Q is always "00". I dont know what is wrong.
Click to expand...
The problem is in your original verilog code.
The conversion to vhdl is irrelevant until the verilog is debugged.

-- Mike Treseler
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top