K
Kuan Zhou
Guest
Hi,
I am using Cadence 5.0.33.011305 on Fedora 2 to simulate my
schematics. But spectre gives me the following warning message:
Warning from spectre during AHDL read-in.
"/cad/cds/IBM_PDK/cmrf7sf/relML/Spectre/models/mvcap.va", line 11:
Warning: (Archaic Syntax) Does not comply with the Accellera Verilog-AMS
2.0 Standard and beyond. To comply with the current standard, use a
larger number in place of `inf'. `inf' is now used only to specify
ranges.
"/cad/cds/IBM_PDK/cmrf7sf/relML/Spectre/models/mvcap.va", line 19:
WarningArchaic Syntax) Does not comply with the Accellera Verilog-AMS
2.0 Standard and beyond. To comply with the current standard, assign a
value to `T'. A variable that is never assigned a value is
considered a digital variable in Verilog-AMS and is therefore not pure
Verilog-A.
How can I remove such warning messages? I used the same Cadence on
Redhat 8 in another machine and got no warning message. But redhat 8
doesn't support my SATA harddisk and audio chip.
Kuan
I am using Cadence 5.0.33.011305 on Fedora 2 to simulate my
schematics. But spectre gives me the following warning message:
Warning from spectre during AHDL read-in.
"/cad/cds/IBM_PDK/cmrf7sf/relML/Spectre/models/mvcap.va", line 11:
Warning: (Archaic Syntax) Does not comply with the Accellera Verilog-AMS
2.0 Standard and beyond. To comply with the current standard, use a
larger number in place of `inf'. `inf' is now used only to specify
ranges.
"/cad/cds/IBM_PDK/cmrf7sf/relML/Spectre/models/mvcap.va", line 19:
WarningArchaic Syntax) Does not comply with the Accellera Verilog-AMS
2.0 Standard and beyond. To comply with the current standard, assign a
value to `T'. A variable that is never assigned a value is
considered a digital variable in Verilog-AMS and is therefore not pure
Verilog-A.
How can I remove such warning messages? I used the same Cadence on
Redhat 8 in another machine and got no warning message. But redhat 8
doesn't support my SATA harddisk and audio chip.
Kuan