Simulation problem in CVER - why not answer our support emai

[Steve Meyer]

Please do not post bug reports to the comp.lang.verilog news group
without first replying to our support question email (see copy of
your original post at bottom of this post). We emailed our standard reply
asking you to either compile a version of Cver with -g and send us the gdb
back trace or send us a failing test case (see original bug report email
below). We did not receive a reply, but instead you posted a message to
comp.lang.verilog that also provided no details.

We will gladly help solve your simulation problem if you send us the
requested information.

We believe Cver is well supported and even sell commericial support
so we do not understand your problem.
/Steve

P.S. Sorry if this message has already been posted. It was posted
using our building's LAN news server and seems not to have been posted.
It is not findable using Google group search.

==========================================
ORIGINAL EMAIL:

Quoting "Balaji Nagarajan":

Hello sir

I have been evaluating CVER for some time. I believe that CVER would be
a very good and stable simulator. I am using CVER under Cygwin.
Recently i tried to compile one of my projects. The CVER is doing a stack dump.
The message is "Status Access violation". From GDB i could see that the
segmentation fault is happening at the following function in CVER source.

__push_itstk()

Is there any memory limitation (How much of memory is required for CVER?).
Is this a known bug? Any help in this regard will be highly appreciated.

Regards

==========================================
POST TO comp.lang.verilog:

Quoting "FairChild" <balajinagarajan@hotmail.com>:

From balajinagarajan@hotmail.com Thu Sep 30 20:10:42 2004
From: "FairChild" <balajinagarajan@hotmail.com
Newsgroups: comp.lang.verilog
Subject: Simulation problem in CVER
Date: Tue, 21 Sep 2004 07:28:50 -0400
Organization: www.talkaboutprogramming.com
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Hi

1) Recently i tried to do functional simualtion of my code, which uses
some Altera primitives (Altdpram), in CVER. I found that the simulator is
doing a core dump. The same is happening with Xilinx BRAM primitive. I am
not sure if these primitives are the real problem. I would like to know if
anyone else have faced the same problem or similar problem (and a way to
solve it )
FYI: I am using CVER in Cygwin environment. I tried the same code in
almost all the recent versions of CVER.

2) I also tried to do timing simulation with the altera library and then
with Xilinx library(i used compiler directive to select the primitives
before synthesis). CVER is having some problem with SDF annotation
(probably i may be having some problem) I could not get them working. I
would like to know if anybody have done timing simulation with CVER. If
yes..what is the procedure. I followed the procedure given in Quartus
handbook.

Thanks




--

Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: sjmeyer@pragmatic-c.com
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402



--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: sjmeyer@pragmatic-c.com
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402