simulation of design + dimm

[Nahum Barnea]

Hi.
I have a design (full xilinx virtex2pro 20) that is connected to a
dimm of 64 MB.

I have a verilog model for the dimm (built from the sdram parts model
from the vendor site).
The verilog simulations are very slow because of the dimm.
There is no way to accelerate the simulation by reducing the size of
dimm.

Is there a known fast sdram model - maybe using PLI ?

ThankX,
NAHUM

 

[Jim Wu]

<nahum_barnea@yahoo.com> wrote in message
news:1109707274.955213.231490@f14g2000cwb.googlegroups.com...

This is very interesting to me.

Does anyone know is a similiar pragma works for modelsim verilog ??

It's in the user guide...

Jim

MysticSage wrote:
Are you accessing whole 64 MB during simulation? Or only few
locations?

Normally all "fast" models are sparse memory models, in which only
"accessed" locations are dynamically allocated. These locations can
be
spread throughout 64 MB address range though. But there is penalty in
terms of overhead for managing these memory location.

Most of the time, only a portion of the memory is used during
simulation, this overhead is not much and it works fine. But if your
simulation is accessing all of the 64 MB locations, overhead will be
significant and it may be significantly slower than your current
simulation. So first see if you can use sparse memory models or not.
You may find some models on the net

VCS also supports this. Look at VCS user guide/manual. Use /*sparse*/
pragma.

Code:
reg /*sparse*/ [31:0] pattern [0:10_000_000];
integer i, j;
initial
begin for (j=1; j<10_000; j=j+1)
for (i=0; i<10_000_000; i=i+1_000)
pattern = i+j;
end
endmodule


That example is from the VCS user's guide, which also states.

Quote:
In simulations of this example this memory model used 4 MB of
machine memory with the /*sparse*/ pragma, 81 MB without it.

Hope it helps.

 

[MysticSage]

Are you accessing whole 64 MB during simulation? Or only few locations?

Normally all "fast" models are sparse memory models, in which only
"accessed" locations are dynamically allocated. These locations can be
spread throughout 64 MB address range though. But there is penalty in
terms of overhead for managing these memory location.

Most of the time, only a portion of the memory is used during
simulation, this overhead is not much and it works fine. But if your
simulation is accessing all of the 64 MB locations, overhead will be
significant and it may be significantly slower than your current
simulation. So first see if you can use sparse memory models or not.
You may find some models on the net

VCS also supports this. Look at VCS user guide/manual. Use /*sparse*/
pragma.

Code:
reg /*sparse*/ [31:0] pattern [0:10_000_000];
integer i, j;
initial
begin for (j=1; j<10_000; j=j+1)
for (i=0; i<10_000_000; i=i+1_000)
pattern = i+j;
end
endmodule


That example is from the VCS user's guide, which also states.

Quote:
In simulations of this example this memory model used 4 MB of
machine memory with the /*sparse*/ pragma, 81 MB without it.

Hope it helps.

 

This is very interesting to me.

Does anyone know is a similiar pragma works for modelsim verilog ??


MysticSage wrote:

Are you accessing whole 64 MB during simulation? Or only few
locations?

Normally all "fast" models are sparse memory models, in which only
"accessed" locations are dynamically allocated. These locations can
be
spread throughout 64 MB address range though. But there is penalty in
terms of overhead for managing these memory location.

Most of the time, only a portion of the memory is used during
simulation, this overhead is not much and it works fine. But if your
simulation is accessing all of the 64 MB locations, overhead will be
significant and it may be significantly slower than your current
simulation. So first see if you can use sparse memory models or not.
You may find some models on the net

VCS also supports this. Look at VCS user guide/manual. Use /*sparse*/
pragma.

Code:
reg /*sparse*/ [31:0] pattern [0:10_000_000];
integer i, j;
initial
begin for (j=1; j<10_000; j=j+1)
for (i=0; i<10_000_000; i=i+1_000)
pattern = i+j;
end
endmodule


That example is from the VCS user's guide, which also states.

Quote:
In simulations of this example this memory model used 4 MB of
machine memory with the /*sparse*/ pragma, 81 MB without it.

Hope it helps.

 

[Nahum Barnea]

ThankX, I've found it.

Its the same /*sparse*/ for modelsim 6.0c




"Jim Wu" <nospam@nospam.com> wrote in message news:<d035rp$1ai2@cliff.xsj.xilinx.com>...

nahum_barnea@yahoo.com> wrote in message
news:1109707274.955213.231490@f14g2000cwb.googlegroups.com...

This is very interesting to me.

Does anyone know is a similiar pragma works for modelsim verilog ??

It's in the user guide...

Jim




MysticSage wrote:
Are you accessing whole 64 MB during simulation? Or only few
locations?

Normally all "fast" models are sparse memory models, in which only
"accessed" locations are dynamically allocated. These locations can
be
spread throughout 64 MB address range though. But there is penalty in
terms of overhead for managing these memory location.

Most of the time, only a portion of the memory is used during
simulation, this overhead is not much and it works fine. But if your
simulation is accessing all of the 64 MB locations, overhead will be
significant and it may be significantly slower than your current
simulation. So first see if you can use sparse memory models or not.
You may find some models on the net

VCS also supports this. Look at VCS user guide/manual. Use /*sparse*/
pragma.

Code:
reg /*sparse*/ [31:0] pattern [0:10_000_000];
integer i, j;
initial
begin for (j=1; j<10_000; j=j+1)
for (i=0; i<10_000_000; i=i+1_000)
pattern = i+j;
end
endmodule


That example is from the VCS user's guide, which also states.

Quote:
In simulations of this example this memory model used 4 MB of
machine memory with the /*sparse*/ pragma, 81 MB without it.

Hope it helps.