simulation of bus cycles

[tullio]

Hi,

i need to simulate the handshaking of a bus in order to comunicate
with my UUT.
Each access (for instance a read) requires a sequence of several
assignements inside an always block.
I need to repeat several times the access.
What's the best way to group together the instructions of the bus cycle
?
Is there anything like the VHDL "procedure" that can handle sequential
statements ?

 

[RobJ]

"tullio" <tullio.grassi@gmail.com> wrote in message
news:1154442678.595894.59510@b28g2000cwb.googlegroups.com...

Hi,

i need to simulate the handshaking of a bus in order to comunicate
with my UUT.
Each access (for instance a read) requires a sequence of several
assignements inside an always block.
I need to repeat several times the access.
What's the best way to group together the instructions of the bus cycle
?
Is there anything like the VHDL "procedure" that can handle sequential
statements ?

I use verilog tasks for this kind of thing in test benches.

Rob