Simulation initialization problem

[Tomek]

Hello,
It's the first time I am posting to comp.lang.vhdl,
and I am a complete VHDL beginner, so please bear with me.

Using ActiveHDL's waveform editor I am trying to simulate
a simple NAND gate. The following is an excerpt from the VHDL code:

[...]
input_1 : in bit;
input_2 : in bit;
output : out bit; -- interface declaration;
[...]
output <= not (input_1 and input_2); -- architecture declaration;
[...]

After the simulation is _initialized_, the state of the "output"
port is '0', whereas I expected it to be '1' according to NAND's
truth table. Why doesn't the initialization process initialize
the "output" port?

Thank you very much indeed for all kind comments,

Kindest regards,

Tom

 

[ALuPin]

Are the inputs registered signals with Reset initialization ?

Could you show your complete description ?

tmyslowski@wp.pl (Tomek) wrote in message news:<e7b47f41.0407220121.1fe48487@posting.google.com>...

Hello,
It's the first time I am posting to comp.lang.vhdl,
and I am a complete VHDL beginner, so please bear with me.

Using ActiveHDL's waveform editor I am trying to simulate
a simple NAND gate. The following is an excerpt from the VHDL code:

[...]
input_1 : in bit;
input_2 : in bit;
output : out bit; -- interface declaration;
[...]
output <= not (input_1 and input_2); -- architecture declaration;
[...]

After the simulation is _initialized_, the state of the "output"
port is '0', whereas I expected it to be '1' according to NAND's
truth table. Why doesn't the initialization process initialize
the "output" port?

Thank you very much indeed for all kind comments,

Kindest regards,

Tom

 

[Just an Illusion]

Hi Tomek,

According to your equation, it is possible to obtain 0 'after'
initialization, if both input_1 and input_2 are at '1' (by your test).

Now, what do you call _initialized_ ? At simulation time 0 (before the
first interpretation step), any inputs are 'U' and, according to the
vhdl lrm, any outputs are mapped to the left value of their values' space.
In case of bit that is 0 (with 'bit' values' space are ordered 0,1).

If you replace bit by std_logic, you need obtain 'U' for output.

JaI

Tomek wrote:

Hello,
It's the first time I am posting to comp.lang.vhdl,
and I am a complete VHDL beginner, so please bear with me.

Using ActiveHDL's waveform editor I am trying to simulate
a simple NAND gate. The following is an excerpt from the VHDL code:

[...]
input_1 : in bit;
input_2 : in bit;
output : out bit; -- interface declaration;
[...]
output <= not (input_1 and input_2); -- architecture declaration;
[...]

After the simulation is _initialized_, the state of the "output"
port is '0', whereas I expected it to be '1' according to NAND's
truth table. Why doesn't the initialization process initialize
the "output" port?

Thank you very much indeed for all kind comments,

Kindest regards,

Tom

 

[Tomek]

ALuPin wrote:

Are the inputs registered signals with Reset initialization ?

Well, I am not sure I understand (you see, I am a complete novice),
but I have the simulator register all the ports before I run
the simulation.

Could you show your complete description ?

With great pleasure. Thank you very much for your interest.

library ieee;
use ieee.std_logic_1164.all;

entity nand_primitive is

port (input_1 : in bit;
input_2 : in bit;
output : out bit );

end nand_primitive;

architecture nand_primitive of nand_primitive is

begin

output <= not (input_2 and input_1);

end nand_primitive;

Thank you again.

Tom
P.S. As I said, the problem is that after I initialize
the simulation (whatever that causes, and I suspect
it causes the initiatialization of the states of all
the objects in the structure with the leftmost value
of the type they belong to, with no consideration
of the relations they are all part of) the object "output"
is set to zero (regardless of the fact that it is bound
by the NAND relation to objects "input_1" and "input_2").
Thus at time /0 ns/ the value of "output" is reported to be '0', while
after a single step of simulation is taken, the aposteriori
value of object "output" at time /0 ns/ is reported to be '1'.

I perfectly understand, this is all about my mixing things
and not understanding the general compiling and event
scheduling techniques.

 

[Tomek]

Just wrote:

According to your equation, it is possible to obtain 0 'after'
initialization, if both input_1 and input_2 are at '1' (by your test).

Yes, that's right. But the problem is that the output is '0' when the
inputs are '0', where it should be '1'.

Now, what do you call _initialized_ ? At simulation time 0 (before the
first interpretation step), any inputs are 'U' and, according to the
vhdl lrm, any outputs are mapped to the left value of their values' space.

Precisely so. However, the problem is that after the simulation
initialization,
i.e. at time /0 ns/ the output is reported to be non initialized
('U')(given that we choose std_logic as the type of ports' signals),
whereas after a single step of simulation is taken, the output is
reported to have been '1' at time /0 ns/.

In case of bit that is 0 (with 'bit' values' space are ordered 0,1).

That's right. So, what does initialization do? What standard is there?

If you replace bit by std_logic, you need obtain 'U' for output.

Yes. And I get /0 ns/ = 'U' and then /0 ns/ = '1'.

Thank you.

Tom

 

[Thomas Stanka]

Hello,

tmyslowski@wp.pl (Tomek) wrote:

output <= not (input_1 and input_2); -- architecture declaration;
After the simulation is _initialized_, the state of the "output"
port is '0', whereas I expected it to be '1' according to NAND's
truth table. Why doesn't the initialization process initialize
the "output" port?

Ok, thats a question of how a VHDL-simulator works.
The simulator counts not only ns (or fs or whatever you use as
timebase) but also ticks (or deltas). One Tick is an infinitesimal
small amount of time after the last tick. Theorethically you could
have umlimited number of ticks between 0 ns and 1 ns.

Your simulator starts in 0 ns, 0 tick where each output has the value
set in statements like
signal output:std_ulogic :='0'

After that the simulator advances to the next time, where a
signalvalue changes.

The line
out <= in
is a short form for
out <= in AFTER 0 ns

this means, the signal changes during the same time but it can't
change immediately (like it would in variables). So the changes is
scheduled for 0 ns, 1 Tick. If you write out <= in after 1 ns, it
would change in 1 ns, 0 tick.

So you see, that the value changes only after a simulator starts, but
befor the timeline advances to the next timestep.

This simulator behavior should be understand, to see why statements
like

process (value1, value2)
begin
value1<=not value2
value2<=value1
end

slow down your simulator to nearly doing nothing.

process (value1, value2)
begin
value1<=not value2 after 2 ns
value2<=value1 after 2 ns
end

is useable, while both statements generate the same hardware after
synthesis.

bye Thomas

 

[Tomek]

Thomas Stanka wrote:

Ok, thats a question of how a VHDL-simulator works.
The simulator counts not only ns (or fs or whatever you use as
timebase) but also ticks (or deltas). One Tick is an infinitesimal
small amount of time after the last tick. Theorethically you could
have umlimited number of ticks between 0 ns and 1 ns.

[snipped the rest of the most interesting remarks]

Thank you, Thomas. The answer you provided is the one I really expected
(I figured the infinitesimally small time laps would be the issue).

Thank you very much for writing.

Thomas

 

[Rafal Fijolek]

"Tomek" <tmyslowski@wp.pl> wrote in message
news:e7b47f41.0407220121.1fe48487@posting.google.com...

input_1 : in bit;
input_2 : in bit;
output : out bit; -- interface declaration;
[...]
output <= not (input_1 and input_2); -- architecture declaration;
[...]

After the simulation is _initialized_, the state of the "output"
port is '0', whereas I expected it to be '1' according to NAND's
truth table. Why doesn't the initialization process initialize
the "output" port?

When you hit "initialize simulation" in your simulator then all the
simulator does is to apply
initialization values to your signals and ports. VHDL standard defines that
all your ports
should initialize to '0' (in this case) and that's what you see in the
waveform window.
At this time the simulator's stop at time 0 delta 0 (read about delata
concept in VHDL language).
If you expect to see '1' on your output port then you have to apply your
driver for this port.
(Remember that '1' is not your initialization value for the port it's an
output value from your driver for both
inputs being '0' at the time when simulator starts)
The statement which describes your nand gate behavoiur is your driver.
Now to do this in the console window try this command:
"run 0"
(that is 'zero')
that will "move" your simulation time to the end of time zero which would be
at
the end of the last delta time before moving out from time zero. (time 0
delta 1 in this case)
All the drivers would be applied and you will see your '1' in the waveform
and you're still at time zero in your simulation.

To see what I mean try changing initialization values for ports:

input_1 : in bit := '1' ;
input_2 : in bit := '1' ;
output : out bit := '1'

now try to initialize simulation and you can see that all ports are '1' at
time 0 delta 0 but when you do "run 0" then your output will change to '0'
and that is because your drive overwritten your default initialization
value.

Hope this explains this topic a bit,
Rafal

 

[Tomek]

Rafal wrote:

[snipped the interesting lecture]

Rafal,
Thank you very much for writing. It was great to read your competent
remarks. As you know, the commonly available in Poland VHDL books
(to mention Skahill and Zwolinski) do not elaborate much on the delta
calculus, if I may call it that way. It seems you have figured the delta
stuff completely. Would you be kind enough as to suggest some instructive
reading?

Thank you very much in advance.

Tomek