Simulation Efficiency, continous or procedural ?

Guest
Which is more efficient for the Simulation ?

a) using procedural statement in the RTL code

b) using continous assignments in the RTL code

c) no effect

thanks
 
You would have to be more specific.

In general, they should be similar if they perform similar
calculations. However, differences in how they were written could
result in less efficiency one way or the other.
 
Simulation of procedural assignments would be much more efficient, as
continuous assignments are made up of events triggered by changes on
the RHS values. Hence, there's insertion of active events involved,
compared to the former there's a only a linked-list of assignment
statements.

Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

calzinide@yahoo.de wrote:
Which is more efficient for the Simulation ?

a) using procedural statement in the RTL code

b) using continous assignments in the RTL code

c) no effect

thanks
 

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