Simulating Xilinx FIFOs

[Richard]

Hi all,

I am wondering if there is a way to simulate a Xilinx FIFO that is
generated with the FIFO Generator v6.1 as follows:

COMPONENT fifo_generator_v6_1
GENERIC (
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;

...

)

PORT(
CLK : IN std_logic := '0';
BACKUP : IN std_logic := '0';

...

)

ATTRIBUTE box_type : STRING;
ATTRIBUTE box_type OF fifo_generator_v6_1 : COMPONENT IS "black_box";

ATTRIBUTE GENERATOR_DEFAULT : STRING;
ATTRIBUTE GENERATOR_DEFAULT OF fifo_generator_v6_1: COMPONENT IS
"generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a
map_qrvirtex4_to=virtex4 map_qvirtex4_to=virtex4";

Of course when I just simulate my design this is a blackbox. But to see
that I got everything right, I would need to be able to simulate this
core. Is there a simple way to do that?

In the meantime, I used async_fifo_v5_1.vhd to do some testing which has
a similar interface and worked fine. Anyway, I was wondering if there is
something similiar with the fifo_generator_v6_1.

Many thanks!

 

[backhus]

On 27 Okt., 00:54, Richard <Rich...@yahoo.com> wrote:

Hi all,

I am wondering if there is a way to simulate a Xilinx FIFO that is
generated with the FIFO Generator v6.1 as follows:

COMPONENT fifo_generator_v6_1
   GENERIC (
     C_COMMON_CLOCK           : integer  := 0;
     C_COUNT_TYPE             : integer  := 0;

    ...

  )

   PORT(
     CLK                       : IN  std_logic := '0';
     BACKUP                    : IN  std_logic := '0';

  ...

)

ATTRIBUTE box_type : STRING;
ATTRIBUTE box_type OF fifo_generator_v6_1 : COMPONENT IS "black_box";

ATTRIBUTE GENERATOR_DEFAULT : STRING;
ATTRIBUTE GENERATOR_DEFAULT OF fifo_generator_v6_1: COMPONENT IS
"generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a
map_qrvirtex4_to=virtex4 map_qvirtex4_to=virtex4";

Of course when I just simulate my design this is a blackbox. But to see
that I got everything right, I would need to be able to simulate this
core. Is there a simple way to do that?

In the meantime, I used async_fifo_v5_1.vhd to do some testing which has
a similar interface and worked fine. Anyway, I was wondering if there is
something similiar with the fifo_generator_v6_1.

Many thanks!

Hi Richard,
corgen creates a set of files for each generated core.
One is the ngc netlist.
another one or two are instantiation templates (VHDL, verilog or both)
and then there are also wrapper HDL files for simulation, that
instantiate the xilinxcorelib modules for simulation with correctly
set generics.

Normally ISE Project Navigator should handle al this automatically
when you change from implementatioon to simulation,
Of course you have to add the .xco file, which should happen
automatically when you create a new coregen module from ISE.

If you happen to have problems finding the simulation wrapper, it may
be that your prefered HDL language settings are wrong in the PNs
Preferences.

Have a nice simulation
Eilert

 

[Gabor]

On Oct 27, 2:35 am, backhus <goous...@googlemail.com> wrote:

On 27 Okt., 00:54, Richard <Rich...@yahoo.com> wrote:



Hi all,

I am wondering if there is a way to simulate a Xilinx FIFO that is
generated with the FIFO Generator v6.1 as follows:

COMPONENT fifo_generator_v6_1
   GENERIC (
     C_COMMON_CLOCK           : integer  := 0;
     C_COUNT_TYPE             : integer  := 0;

    ...

  )

   PORT(
     CLK                       : IN  std_logic := '0';
     BACKUP                    : IN  std_logic := '0';

  ...

)

ATTRIBUTE box_type : STRING;
ATTRIBUTE box_type OF fifo_generator_v6_1 : COMPONENT IS "black_box";

ATTRIBUTE GENERATOR_DEFAULT : STRING;
ATTRIBUTE GENERATOR_DEFAULT OF fifo_generator_v6_1: COMPONENT IS
"generatecore com.xilinx.ip.fifo_generator_v6_1.fifo_generator_v6_1 -a
map_qrvirtex4_to=virtex4 map_qvirtex4_to=virtex4";

Of course when I just simulate my design this is a blackbox. But to see
that I got everything right, I would need to be able to simulate this
core. Is there a simple way to do that?

In the meantime, I used async_fifo_v5_1.vhd to do some testing which has
a similar interface and worked fine. Anyway, I was wondering if there is
something similiar with the fifo_generator_v6_1.

Many thanks!

Hi Richard,
corgen creates a set of files for each generated core.
One is the ngc netlist.
another one or two are instantiation templates (VHDL, verilog or both)
and then there are also wrapper HDL files for simulation, that
instantiate the xilinxcorelib modules for simulation with correctly
set generics.

Normally ISE Project Navigator should handle al this automatically
when you change from implementatioon to simulation,
Of course you have to add the .xco file, which should happen
automatically when you create a new coregen module from ISE.

If you happen to have problems finding the simulation wrapper, it may
be that your prefered HDL language settings are wrong in the PNs
Preferences.

Have a nice simulation
  Eilert

Some other notes:

If you use the "Project --> New Source..." method of adding a Coregen
module
to the design, you don't really get to see the Coregen project
settings. Using the
ISE GUI, the only way to get to those is either "Tools --> CoreGen" or
by
selecting the "manage cores" property for an .xco file already in your
design.

When generating FIFO cores, always select the structural models for
simulation.
The behavioral models are not only not cycle-accurate, but they are
also broken
for some configurations. For example in the FWFT dual-clock FIFO's I
found
that the behavioral model did not properly set the programmable almost
full
or empty flags.

Regards,
Gabor