simulating xilinx clkdll

  • Thread starter Amontec Team, Laurent Gau
  • Start date
A

Amontec Team, Laurent Gau

Guest
Hi,

I have some troubles simulating a clkdll primitive with modelsim.

I included a clkdll mapping in my VHDL project to do a clk2x and clk4x.
After synthesis, all is working fine about frequency value (I have a 40
- 80 - 160 MHz).

But now I have to simulate all of this with the main design.
BUT how can I simulate CLKDLL without body description of the unisim
library.

For now, I just did a new VHDL architecture for my CLKDLL. But are there
a better solution for simulation!

Best Regards,
Laurent Gauch


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Hi, May be you didn't compile libruary....

If you have ise 5.2 or over then #15338 in Xilinx support...

You can find compxlib.

I can't english...sorry ^^*

Good luck...bye

"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote
in message news:4003e953$1@news.vsnet.ch...
Hi,

I have some troubles simulating a clkdll primitive with modelsim.

I included a clkdll mapping in my VHDL project to do a clk2x and clk4x.
After synthesis, all is working fine about frequency value (I have a 40
- 80 - 160 MHz).

But now I have to simulate all of this with the main design.
BUT how can I simulate CLKDLL without body description of the unisim
library.

For now, I just did a new VHDL architecture for my CLKDLL. But are there
a better solution for simulation!

Best Regards,
Laurent Gauch


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customers drift off to free webmail services install your own
web gateway!
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Click to expand...
 
Thanks ??? for this advice

??? wrote:
Hi, May be you didn't compile libruary....

If you have ise 5.2 or over then #15338 in Xilinx support...

You can find compxlib.

I can't english...sorry ^^*

Good luck...bye

"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote
in message news:4003e953$1@news.vsnet.ch...

Hi,

I have some troubles simulating a clkdll primitive with modelsim.

I included a clkdll mapping in my VHDL project to do a clk2x and clk4x.
After synthesis, all is working fine about frequency value (I have a 40
- 80 - 160 MHz).

But now I have to simulate all of this with the main design.
BUT how can I simulate CLKDLL without body description of the unisim
library.

For now, I just did a new VHDL architecture for my CLKDLL. But are there
a better solution for simulation!

Best Regards,
Laurent Gauch


------------ And now a word from our sponsor ------------------
Do your users want the best web-email gateway? Don't let your
customers drift off to free webmail services install your own
web gateway!
-- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----
Click to expand...
 
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