K
kvaddina
Guest
Dear all,
I am having a problem simulating Verilog-A model using spectre.
I have added my Verilog-A symbol to my circuit(8-bit Adder) and now
wanted to check whether the Verilog-A model does what it is suppossed
to do. When I try to simulate it (Transient mode..) it gives me the
following error.
Running Artist Hierarchical Netlisting ...
ERROR: Netlister: unable to descend into any of the views defined in
the view list: "spectreS cmos_sch schematic" for instance I5 in cell
Add_rpl_8.
Either add one of these views to: Library:MyLib Cell:GlitchAnalyzer or
modify the view list to contain an existing view.
End netlisting Apr 28 18:59:57 2005
"Netlister: There were errors, no netlist was produced."
...unsuccessful.
...unsuccessful.
Can some one help me out. I am a Newbie to cadence.
Thanks and Regards,
kvaddina.
I am having a problem simulating Verilog-A model using spectre.
I have added my Verilog-A symbol to my circuit(8-bit Adder) and now
wanted to check whether the Verilog-A model does what it is suppossed
to do. When I try to simulate it (Transient mode..) it gives me the
following error.
Running Artist Hierarchical Netlisting ...
ERROR: Netlister: unable to descend into any of the views defined in
the view list: "spectreS cmos_sch schematic" for instance I5 in cell
Add_rpl_8.
Either add one of these views to: Library:MyLib Cell:GlitchAnalyzer or
modify the view list to contain an existing view.
End netlisting Apr 28 18:59:57 2005
"Netlister: There were errors, no netlist was produced."
...unsuccessful.
...unsuccessful.
Can some one help me out. I am a Newbie to cadence.
Thanks and Regards,
kvaddina.